参数资料
型号: MPC9330FA
厂商: MOTOROLA INC
元件分类: 时钟产生/分配
英文描述: 120 MHz, OTHER CLOCK GENERATOR, PQFP32
封装: LQFP-32
文件页数: 4/10页
文件大小: 148K
代理商: MPC9330FA
MPC9330
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
80
Table 1: PIN CONFIGURATION
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
XTAL_IN, XTAL_OUT
Input
Analog
Crystal oscillator interface
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
FB_SEL
Input
LVCMOS
Feedback select
REF_SEL
Input
LVCMOS
Reference clock select
PWR_DN
Input
LVCMOS
Output frequency and power down select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
CLK_STOP0-1
Input
LVCMOS
Clock output enable/disable
OE/MR
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0-1, QB0-1, QC0-1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external
RC filter for the analog power supply pin VCC_PLL. Please see applications section for
details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation
Table 2: FUNCTION TABLE
Control
Default
0
1
REF_SEL
0
The crystal oscillator output is the PLL reference clock
CCLK is the PLL reference clock
FB_SEL
0
Internal PLL feedback of 16. fVCO = 16 * fref
External feedback. Zero-delay operation
enabled for CCLK as reference clock
PLL_EN
1
Test mode with PLL disabled. The reference clock is
substituted for the internal VCO output. MPC9330 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Normal operation mode with PLL
enabled.
PWR_DN
1
VCO
÷ 2 (High output frequency range)
VCO
÷ 4 (Low output frequency range)
FSELA
0
Output divider
÷ 2
Output divider
÷ 4
FSELB
0
Output divider
÷ 2
Output divider
÷ 4
FSELC
0
Output divider
÷ 4
Output divider
÷ 6
CLK_STOP[0:1]
11
See Table 3
OE/MR
1
Outputs disabled (high-impedance state) and reset of the
device. During reset in external feedback configuration, the
PLL feedback loop is open. The VCO is tied to its lowest
frequency. The MPC9330 requires reset after any loss of PLL
lock. Loss of PLL lock may occur when the external feedback
path is interrupted. The length of the reset pulse should be
greater than one reference clock cycle (CCLK). Reset does
not affect PLL lock in internal feedback configuration.
Outputs enabled (active)
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Tables 10–12 for supported frequency ranges and output to input frequency ratios.
2
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