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参数资料
| 型号： | MPC9330FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 120 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 9/10页 |
| 文件大小： | 148K |
| 代理商： | MPC9330FA |
MPC9330
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
85
APPLICATIONS INFORMATION
Power Supply Filtering
The MPC9330 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9330 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCC_PLL) of the device. The purpose of this design tech-
nique is to isolate the high switching noise digital outputs from
the relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCC_PLL pin for the MPC9330. Figure 3
illustrates a typical power supply filter scheme. The MPC9330
frequency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
sheet the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 5 mA (10 mA maximum), assuming
that a minimum of 2.985V must be maintained on the VCC_PLL
pin. The resistor RF shown in Figure 3 ”VCC_PLL Power Supply
Filter” should have a resistance of 10–15
W to meet the voltage
drop criteria.
Figure 3. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC9330
10 nF
RF = 10 - 15
CF
33...100 nF
RF
VCC
CF = 22 F
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3 “VCC_PLL Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low im-
pedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9330 has several de-
sign features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be ade-
quate to eliminate power supply noise related problems in
most designs.
Driving Transmission Lines
The MPC9330 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the meth-
od of choice. In a point-to-point scheme either series termi-
nated or parallel terminated transmission lines can be used.
The parallel technique terminates the signal at the end of the
line with a 50
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9330 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can
drive multiple series terminated lines. Figure 4 “Single versus
Dual Transmission Lines” illustrates an output driving a single
series terminated line versus two series terminated lines in
parallel. When taken to its extreme the fanout of the MPC9330
clock driver is effectively doubled due to its capability to drive
multiple lines.
Figure 4. Single versus Dual Transmission Lines
14
IN
MPC9330
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC9330
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots in Figure 5 “Single versus Dual Line
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases the
drive capability of the MPC9330 output buffer is more than suf-
ficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output-to-output skew of the
MPC9330. The output waveform in Figure 5 “Single versus
Dual Line Termination Waveforms” shows a step in the wave-
form, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36
se-
ries resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
2
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