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参数资料
| 型号： | MPC950FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 180 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, LQFP-32 |
| 文件页数： | 10/10页 |
| 文件大小： | 131K |
| 代理商： | MPC950FAR2 |
MPC950
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
158
Figure 9. PLL Block Diagram
fref
Phase
Detector
Qn
VCO
LPF
÷P
÷N
÷m
N fref +
fQn N P
m
fref +
fVCO
m
,fVCO + fQn N P
m = 8 (FBsel = ‘1’), 16(FBsel = ‘0’)
P = 1
For the MPC950 clock driver, the following will provide an
example of how to determine the crystal frequency required for
a given design.
Given:
Qa
= 160MHz
Qb
= 80MHz
Qc
= 40MHz
Qd
= 40MHz
FBSel = ‘0’
fref +
fQn N P
m
From Table 3
fQd = VCO/8 then N = 8 OR fQa = VCO/2 then N = 2
From Figure 9
m = 16 and P = 1
fref +
40 81
16
+ 20MHz OR
160 2 1
16
+ 20MHz
Driving Transmission Lines
The MPC950 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To pro-
vide the optimum flexibility to the user the output drivers were
designed to exhibit the lowest impedance possible. With an
output impedance of approximately 10
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50
resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC950 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 10 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC950 clock driver is effectively doubled due to its
capability to drive multiple lines.
Figure 10. Single versus Dual Transmission Lines
7
IN
MPC950
OUTPUT
BUFFER
RS = 43
ZO = 50
OutA
7
IN
MPC950
OUTPUT
BUFFER
RS = 43
ZO = 50
OutB0
RS = 43
ZO = 50
OutB1
The waveform plots of Figure 11 show the simulation results
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC950 output buffers is more than suf-
ficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC950. The output waveform in Figure 11 shows a step in
the waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
43
series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50
|| 50
Rs = 43
|| 43
Ro = 7
VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)
= 1.40V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
2
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