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参数资料
| 型号： | MPC950FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 180 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, LQFP-32 |
| 文件页数： | 8/10页 |
| 文件大小： | 131K |
| 代理商： | MPC950FAR2 |
MPC950
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
156
Figure 5. PLL Jitter and Edge Displacement
1
212
12
1
232
12
3
Peak-to-Peak PLL Jitter
Peak-to-Peak Period Jitter
Peak-to-Peak PLL Jitter
Peak-to-Peak Period Jitter
Figure 6 graphically represents the PLL jitter of the
MPC950. The data was taken for several different output con-
figurations. By triggering on the lowest frequency output the
PLL jitter can be measured for configurations in which outputs
are switching at different frequencies. As one can see in the
figure the PLL jitter is much less dependent on output configu-
ration than on internal VCO frequency.
Two different configurations were chosen to look at the peri-
od displacement caused by the switching outputs. Configura-
tion 3 is considered worst case as the “trimodal” distribution
(as pictured in Figure 5) represents the largest spread be-
tween distribution peaks. Configuration 2 is considered a typi-
cal configuration with half the outputs at a high frequency and
the remaining outputs at one half the high frequency. For these
cases the peak–to–peak numbers are reported in Figure 7 as
the sigma numbers are useless because the distributions are
not Gaussian. For situations where the outputs are synchro-
nous and switching at different frequencies the measurement
technique described here is insufficient to use for establishing
guaranteed limits. Other techniques are currently being inves-
tigated to identify a more accurate and repeatable measure-
ment so that guaranteed limits can be provided. The data gen-
erated does give a good indication of the general performance,
a performance that in most cases is well within the require-
ments of today’s microprocessors.
Figure 6. RMS PLL Jitter versus VCO Frequency
0
5
10
15
20
25
30
35
40
160
240
320
400
480
560
Conf 1
Conf 2
Conf 3
Conf 1 = All Outputs at the Same Frequency
Conf 2 = 4 Outputs at X, 5 Outputs at X/2
Conf 3 = 1 Output at X, 8 Outputs at X/4
VCO Frequency (MHz)
RMS
Jitter
(ps)
Figure 7. Peak–to–Peak Period Jitter versus
VCO Frequency
150
200
250
300
350
400
160
240
320
400
480
560
Conf 2
Conf 3
Conf 2 = 4 Outputs at X, 5 Outputs at X/2
Conf 3 = 1 Output at X, 8 Outputs at X/4
VCO Frequency (MHz)
Paek-to-Peak
Jitter
(ps)
Finally from the data there are some general guidelines that,
if followed, will minimize the output jitter of the device. First and
foremost always configure the device such that the VCO runs
as fast as possible. This is by far the most critical parameter in
minimizing jitter. Second keep the reference frequency as high
as possible. More frequent updates at the phase detector will
help to reduce jitter. Note that if there is a tradeoff between
higher reference frequencies and higher VCO frequency al-
ways chose the higher VCO frequency to minimize jitter. The
third guideline may be the most difficult, and in some cases
impossible, to follow. Try to minimize the number of different
frequencies sourced from a single chip. The fixed edge dis-
placement associated with the switching noise in most cases
nearly doubles the “effective” jitter of a high speed output.
Power Supply Filtering
The MPC950 is a mixed analog/digital product and as such
it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally sus-
ceptible to random noise, especially if this noise is seen on the
power supply pins. The MPC950 provides separate power
supplies for the output buffers (VCCO) and the phase–locked
loop (VCCA) of the device. The purpose of this design tech-
nique is to try and isolate the high switching noise digital out-
2
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相关代理商/技术参数 |
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| MPC951 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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