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参数资料
| 型号： | MPC973FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 973 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 13/13页 |
| 文件大小： | 629K |
| 代理商： | MPC973FA |
MPC973
9
MOTOROLA
`0'
MPC973
Figure 8. Programming Configuration Example
fsela0
`0'
fsela1
fselb0
fselb1
Input Ref
50MHz
fselc0
fselc1
fselFB0
fselFB1
fselFB2
VCO = 400MHz
Ext_FB
100 MHz
Qa
40 MHz
Qb
66.66 MHz
Qc
4
50 MHz
QFB
`1'
`0'
`1'
`0'
`1'
`0'
MPC973
Figure 9. Generating Pentium Clocks from Floppy Clock
fsela0
`0'
fsela1
fselb0
fselb1
Input Ref
24MHz
fselc0
fselc1
fselFB0
fselFB1
fselFB2
Ext_FB
60 MHz (Processor)
Qa
60 MHz (Processor)
Qb
30 MHz (PCI)
Qc
4
24 MHz (Floppy Disk Clk)
QFB
`0'
`1'
`0'
`1'
MPC973
Figure 10. Generating MPC604 Clocks from Ethernet Clocks
fsela0
`1'
fsela1
fselb0
fselb1
Input Ref
20MHz
fselc0
fselc1
fselFB0
fselFB1
fselFB2
Ext_FB
33 MHz (PCI)
Qa
50 MHz (Processor)
Qb
50 MHz (Processor)
Qc
4
20 MHz (Ethernet)
QFB
`0'
`1'
Figure 11. Phase Delay Using Multiple MPC973’s
`0'
MPC973
fsela0
`0'
fsela1
fselb0
fselb1
Input Ref
66MHz
fselc0
fselc1
fselFB0
fselFB1
fselFB2
Ext_FB
66 MHz
Qa
66 MHz
Qb
66 MHz
Qc
4
2
QFB
`0'
`1'
`0'
`1'
MPC973
fsela0
`0'
fsela1
fselb0
fselb1
Input Ref
fselc0
fselc1
fselFB0
fselFB1
fselFB2
Ext_FB
33 MHz Shifted 90°
Qa
33 MHz Shifted 90°
Qb
33 MHz Shifted 90°
Qc
4
66 MHz
QFB
`0'
`1'
`0'
Inv_Clk
`1'
Inv_Clk
`0'
66 MHz
Qc
2
66 MHz
33 MHz
Shifted 90°
66 MHz
Recommended External Reset Timing
For MPC973 applications requiring synchronization of the
output clock to the input clock and if fselFB2 = 1, the assertion
of the MR is recommended. The timing of asserting MR should
be as shown in Figure 12. The power supply should be at or
above the minimum specified voltage and the reference clock
input (refclk) should be present a minimum of t1 prior to the
reset pulse being applied to the MR pin.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MPC973
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC973
9
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相关代理商/技术参数 |
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|---|---|
| MPC974 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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| MPC9772 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V 1:12 LVCMOS PLL Clock Generator |
| MPC9772AE | 功能描述:锁相环 - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9772AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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