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| 型号： | MPC973FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 973 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 2/13页 |
| 文件大小： | 629K |
| 代理商： | MPC973FA |
MPC973
10
MOTOROLA
Figure 12. Assertion of MR
refclk
VDD Power
MR
VDD -5%
t1
t2
t1 > 10 msec
10 ns < t2 <20 ns
Power Supply Filtering
The MPC973 is a mixed analog/digital product and exhibits
some sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The MPC973 provides separate power supplies for
the output buffers (VCCO) and the internal PLL (VCCA) of the
device. The purpose of this design technique is to try and isolate
the high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board this level of isolation
is sufficient. However, in a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the
MPC973.
Figure 13. Power Supply Filter
VCCA
VCC
MPC973
0.01 F
22 F
0.01 F
3.3 V
RS=5-10
Figure 13 illustrates a typical power supply filter scheme. The
MPC973 is most susceptible to noise with spectral content in
the 1 KHz to 1 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs to
be met in the final filter design is the DC voltage drop that will
be seen between the VCC supply and the VCCA pin of the
MPC973. From the data sheet the IVCCA current (the current
sourced through the VCCA pin) is typically 15 mA (20 mA
maximum), assuming that a minimum of 2.935 V must be
maintained on the VCCA pin very little DC voltage drop can be
tolerated when a 3.3 V VCC supply is used. The resistor shown
in Figure 13 must have a resistance of 5–10
to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for noise
whose spectral content is above 20 KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the bandwidth
of the PLL.
Although the MPC973 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
Driving Transmission Lines
The MPC973 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of approximately 10
the drivers can
drive either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC973 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 14 illustrates an output driving a single series terminated
line vs two series terminated lines in parallel. When taken to its
extreme the fanout of the MPC973 clock driver is effectively
doubled due to its capability to drive multiple lines.
Figure 14. Single versus Dual Transmission Lines
7
IN
MPC973
OUTPUT
BUFFER
RS = 43
ZO = 50
OutA
7
IN
MPC973
OUTPUT
BUFFER
RS = 43
ZO = 50
OutB0
RS = 43
ZO = 50
OutB1
The waveform plots of Figure 15 show the simulation results
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC973 output buffers is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MPC973
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC973
10
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| MPC9772AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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