参数资料
型号: MPC9773AE
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封装: 10 X 10 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, LQFP-52
文件页数: 12/19页
文件大小: 1007K
代理商: MPC9773AE
Advanced Clock Drivers Device Data
2
Freescale Semiconductor
MPC9773
Figure 1. MPC9773 Logic Diagram
Figure 2. MPC9773 52-Lead Package Pinout (Top View)
PLL
÷4, ÷6, ÷8, ÷12
0
1
0
1
0
1
0
QFB
QSYNC
12
3
2
All input resistors have a value of 25 k
1
0
PCLK
CCLK0
CCLK1
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
INV_CLK
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
Bank A
Bank B
Bank C
Clock Stop
VCO
Ref
FB
SYNC PULSE
÷4, ÷6, ÷8, ÷10
÷12, ÷16, ÷20
÷2, ÷4, ÷6, ÷8
÷4, ÷6, ÷8, ÷10
QC2
QC3
FSEL_FB[0:2]
STOP_DATA
STOP_CLK
MR/OE
CCLK_SEL
REF_SEL
FB_IN
VCO_SEL
PLL_EN
VCC
200–485 MHz
CLK
Stop
CLK
Stop
CLK
Stop
CLK
Stop
CLK
Stop
VCC
÷2
÷1
Power-On Reset
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VCC
QA2
GND
QA1
VCC
QA0
GND
VCO_SEL
FSEL_FB1
QSYNC
GND
QC0
VCC
QC1
FSEL_C0
FSEL_C1
QC2
VCC
QC3
GND
INV_CLK
GND
QB0
V
CC
QB1
GND
QB2
V
CC
QB3
FB
_I
N
GND
QF
B
V
CC
FSEL_FB
0
GND
MR
/OE
STOP_C
LK
STOP_DA
TA
FSEL_F
B2
PLL_
EN
REF_S
EL
CCLK_S
EL
CCL
K0
CCL
K1
V
CC_PLL
PC
LK
PC
LK
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
NETCOM
IDT 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
2
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