- 您现在的位置：买卖IC网 > PDF目录29137 > MPC9773AE (INTEGRATED DEVICE TECHNOLOGY INC) 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 PDF资料下载
参数资料
| 型号： | MPC9773AE |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, LQFP-52 |
| 文件页数： | 16/19页 |
| 文件大小： | 1007K |
| 代理商： | MPC9773AE |
Advanced Clock Drivers Device Data
6
Freescale Semiconductor
MPC9773
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C)(1), (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input Reference Frequency
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
Input Reference Frequency in PLL Bypass Mode
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
121.2
80.8
60.6
48.5
40.4
30.3
24.2
20.2
15.1
12.1
250
MHz
PLL locked
PLL bypass
fVCO
VCO Frequency Range
200
485
MHz
fMAX
Output Frequency
÷ 2 output
÷ 4 output
÷ 6 output
÷ 8 output
÷ 10 output
÷ 12 output
÷ 16 output
÷ 20 output
÷ 24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
242.5
121.2
80.8
60.6
48.5
40.4
30.3
24.2
20.2
MHz
PLL locked
fSTOP_CLK
Serial Interface Clock Frequency
20
MHz
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
400
1000
mV
LVPECL
VCMR
Common Mode Range(3)
PCLK, PCLK
1.2
VCC – 0.9
V
LVPECL
tPW,MIN
Input Reference Pulse Width(4)
2.0
ns
tR, tF
CCLKx Input Rise/Fall Time(5)
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay (static phase offset)(6)
6.25 MHz < fREF < 65.0 MHz
65.0 MHz < fREF < 125 MHz
fREF = 50 MHz and feedback = ÷8
–3
–4
–166
+3
+4
+166
°
ps
PLL locked
tSK(O)
Output-to-Output Skew(7)
within QA outputs
within QB outputs
within QC outputs
all outputs
100
250
ps
DC
Output Duty Cycle(8)
(T
÷2) –200
T
÷2
(T
÷2) +200
ps
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
8.0
ns
tPZL, LZ
Output Enable Time
8.0
ns
tJIT(CC)
Cycle-to-cycle Jitter(9)
150
ps
tJIT(PER)
Period Jitter(10)
100
ps
tJIT()
I/O Phase Jitter RMS (1
σ)(11)
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
11
86
13
88
16
19
21
22
27
30
ps
(VCO = 400 MHz)
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
NETCOM
IDT 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
6
相关PDF资料 |
PDF描述 |
|---|---|
| MPC97H74AER2 | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H74FAR2 | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H74FA | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9893FAR2 | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| MPC991FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9773AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773FA | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9773FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 52-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9773FAR2 - Tape and Reel |
| MPC9774 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC9774AE | 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
发布紧急采购，3分钟左右您将得到回复。