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| 型号： | MPC9773AE |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, LQFP-52 |
| 文件页数： | 4/19页 |
| 文件大小： | 1007K |
| 代理商： | MPC9773AE |
Advanced Clock Drivers Device Data
12
Freescale Semiconductor
MPC9773
Due to the statistical nature of I/O jitter, an RMS value (1
σ) is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 12.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
Due to the frequency dependence of the static phase
offset and I/O jitter, using Figure 9 to Figure 11 to predict a
maximum I/O jitter and the specified t() parameter relative to
the input reference frequency results in a precise timing
performance analysis.
In the following example calculation an I/O jitter confidence
factor of 99.7% (
± 3σ) is assumed, resulting in a worst-case
timing uncertainty from the common input reference clock to
any output of –455 ps to +455 ps relative to CCLK (PLL
feedback =
÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps RMS max., static
phase offset t() = ± 166 ps):
tSK(PP) = [–166ps...166ps] + [–250ps...250ps] +
[(13ps
–3)...(13ps 3)] + tPD, LINE(FB)
tSK(PP) = [–455ps...455ps] + tPD, LINE(FB)
Figure 9. MPC9773 I/O Jitter
Figure 10. MPC9773 I/O Jitter
Figure 11. MPC9773 I/O Jitter
Driving Transmission Lines
The MPC9773 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high-performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50-
resistance to VCC ÷ 2.
Table 12. Confidence Factor CF
CF
Probability of Clock Edge
within the Distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
VCO frequency [MHz]
200
250
300
350
400
450 480
160
140
120
100
80
60
40
20
0
FB =
÷32
FB =
÷16
FB =
÷8
FB =
÷4
Maximum I/O Phase Jitter versus Frequency Parameter:
PLL Feedback Divider FB
t jit
[φ
][p
s]
RMS
VCO frequency [MHz]
200
250
300
350
400
450 480
120
100
80
60
40
20
0
FB =
÷12
FB =
÷24
Maximum I/O Phase Jitter versus Frequency Parameter:
PLL Feedback Divider FB
FB =
÷6
t jit
[φ
][p
s]
RMS
VCO frequency [MHz]
200
250
300
350
400
450
480
140
120
100
80
60
40
20
0
FB =
÷20
FB =
÷10
FB =
÷40
Maximum I/O Phase Jitter versus Frequency Parameter:
PLL Feedback Divider FB
t jit[
φ]
[p
s]
RMS
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
NETCOM
IDT 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
12
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| MPC9773AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773FA | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9773FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 52-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9773FAR2 - Tape and Reel |
| MPC9774 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC9774AE | 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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