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参数资料
| 型号： | MPC97H73FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 1/20页 |
| 文件大小： | 206K |
| 代理商： | MPC97H73FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC97H73/D
Rev 0, 10/2003
1
Motorola, Inc. 2003
3.3V 1:12 LVCMOS PLL Clock
Generator
The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With
output frequencies up to 240 MHz and output skews less than 250 ps the
device meets the needs of the most demanding clock applications.
Features
1:12 PLL based low-voltage clock generator
3.3V power supply
Internal power–on reset
Generates clock signals up to 240 MHz
Maximum output skew of 250 ps
Differential PECL reference clock input
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Synchronous output clock stop circuitry for each individual output for
power down support
Drives up to 24 clock lines
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC973
Functional Description
The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.
The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12
outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In
addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a
non–binary factor. The MPC97H73 also supports the 180
° phase shift of one of its output banks with respect to the other output
banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation
of system baseline timing signals.
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass
configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC97H73. The MPC97H73 has an internal power–on reset.
The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
W transmission
lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
MPC97H73
3.3V 1:12 LVCMOS
PLL CLOCK GENERATOR
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相关代理商/技术参数 |
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|---|---|
| MPC97H74AE | 功能描述:时钟发生器及支持产品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC97H74AER2 | 功能描述:时钟发生器及支持产品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC97H74FA | 功能描述:IC PLL CLK GENERATOR 1:14 52LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MPC980 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:DUAL 3.3V PLL CLOCK GENERATOR |
| MPC9817 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers |
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