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参数资料
| 型号： | MPC97H73FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 7/20页 |
| 文件大小： | 206K |
| 代理商： | MPC97H73FAR2 |
MPC97H73
TIMING SOLUTIONS
15
MOTOROLA
Figure 17. Output–to–output Skew tSK(O)
Figure 18. Propagation delay (t(), static phase
offset) test reference
Figure 19. Output Duty Cycle (DC)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCCB2
GND
VCC
VCCB2
GND
tSK(O)
VCC
VCCB2
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCCB2
GND
VCC
VCCB2
GND
t()
CCLKx
FB_IN
TJIT() = |T0-T1mean|
CCLKx
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 20. I/O Jitter
Figure 21. Cycle–to–cycle Jitter
Figure 22. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TN
TJIT(CC) = |TN-TN+1|
TN+1
TJIT(PER) = |TN-1/f0|
T0
tF
tR
VCC=3.3V
2.4
0.55
Figure 23. Output Transition Time Test Reference
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| MPC97H74AER2 | 功能描述:时钟发生器及支持产品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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