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参数资料
| 型号： | MPC97H73FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 17/20页 |
| 文件大小： | 206K |
| 代理商： | MPC97H73FAR2 |
MPC97H73
MOTOROLA
TIMING SOLUTIONS
6
Table 10. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input reference frequency
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
Input reference frequency in PLL bypass mode
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
250
MHz
PLL locked
PLL bypass
fVCO
VCO frequency rangec
200
480
MHz
fMAX
Output Frequency
÷2 output
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
PLL locked
fSTOP_CLK
Serial interface clock frequency
20
MHz
VPP
Peak-to-peak input voltage
PCLK, PCLK
400
1000
mV
LVPECL
VCMRd
Common Mode Range
PCLK, PCLK
1.2
VCC-0.9
V
LVPECL
tPW,MIN
Input Reference Pulse Widthd
2.0
ns
tR, tF
CCLKx Input Rise/Fall Timee
1.0
ns
0.8 to 2.0V
t()
Propagation Delay (static phase offset)f
6.25 MHz < fREF < 65.0 MHz
65.0 MHz < fREF < 125 MHz
fREF=50 MHz and feedback=÷8
-3
-4
-166
+3
+4
+166
°
ps
PLL locked
tSK(O)
Output-to-output Skewg
within QA outputs
within QB outputs
within QC outputs
all outputs
100
250
ps
DC
Output Duty Cycleh
(T
÷2) - 200
T
÷2
(T
÷2) +200
ps
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
8.0
ns
tPZL, LZ
Output Enable Time
8.0
ns
tJIT(CC)
Cycle-to-cycle jitteri
150
200
ps
tJIT(PER)
Period Jitterj
150
ps
tJIT()
I/O Phase Jitter RMS (1
σ)k
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
(VCO=400 MHz)
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