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参数资料
| 型号： | MPC9991FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 10/16页 |
| 文件大小： | 215K |
| 代理商： | MPC9991FAR2 |
MPC9991
TIMING SOLUTIONS
3
MOTOROLA
Figure 2. MPC9991 52–Lead Package Pinout (Top View)
QB3
VCC
QA0
QA1
QA2
QA3
SYNC_SEL
VCO_SEL
QC1
QCO
QC0
VCC
QD1
QD0
VCC
QFB
VCC_PLL
FSEL0
QB2
FSEL1
QB1
FSEL2
QB0
VCC
QC2
FSEL3
VEE
MR
PLL_EN
REF_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
TCLK
ECLK
VCC
FB_IN
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
12
34
56
78
9
10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MPC9991
Table 1: PIN CONFIGURATION
Pin
I/O
Type
Function
ECLK, ECLK
Input
PECL/ECL
Differential reference clock signal input
TCLK
Input
PECL/ECL
Single-ended test clock input
FB_IN, FB_IN
Input
PECL/ECL
Differential PLL feedback clock signal input, connect to QFB, QFB
VCO_SEL
Input
PECL/ECL
VCO operating frequency select
PLL_EN
Input
PECL/ECL
PLL Enable/Bypass mode select
REF_SEL
Input
PECL/ECL
PLL reference signal input select
MR
Input
PECL/ECL
Device reset
FSEL[3:0]
Input
PECL/ECL
Output frequency divider select
FSEL_FB[2:0]
Input
PECL/ECL
Frequency divider select for the QFB output
SYNC_SEL
Input
PECL/ECL
QD output mode select
QA[0-3], QA[0-3]
Output
PECL/ECL
Differential clock outputs (bank A)
QB[0-3], QB[0-3]
Output
PECL/ECL
Differential clock outputs (bank B)
QC[0-2], QC[0-2]
Output
PECL/ECL
Differential clock outputs (bank C)
QD[0-1], QD[0-1]
Output
PECL/ECL
Differential clock/SYNC signal outputs (bank D)
QFB, QFB
Output
PECL/ECL
Differential PLL feedback clock output (connect to FB_IN, FB_IN)
VEEa
Supply
VEE
Negative power supply
VCC
Supply
VCC
Positive power supply. All VCC pins must be connected to the positive power supply for
correct DC and AC operation
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external
RC filter for the analog power supply pin VCC_PLL. Please see applications section for
details
a.
In ECL mode (negative power supply mode), VEE is -3.3V and VCC is connected to GND (0V).
In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is +3.3V.
In both modes, the input and output levels are referenced to the most positive supply (VCC).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992ACR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992FA | 功能描述:锁相环 - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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