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参数资料
| 型号： | MPC9991FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 14/16页 |
| 文件大小： | 215K |
| 代理商： | MPC9991FAR2 |
MPC9991
TIMING SOLUTIONS
7
MOTOROLA
Table 8: AC CHARACTERISTICS (ECL: VEE = –3.3V ± 5%, VCC = GND, or PECL: VCC = 3.3V ± 5%, VEE = GND,
TA = 0°C to 70°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency
÷4 feedback
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
÷64 feedback
÷96 feedback
÷128 feedback
Input reference frequency in PLL bypass modec
200.0
100.0
66.6
50.0
33.3
25.0
16.6
12.5
8.3
6.25
400.0
200.0
133.3
100.0
66.6
50.0
33.3
25.0
16.6
12.5
TBD
MHz
PLL locked
PLL bypass
fVCO
VCO frequency ranged
800
1600
MHz
fMAX
Output Frequency
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
÷32 output
200.0
100.0
66.6
50.0
33.3
25.0
400.0
200.0
133.3
100.0
66.6
50.0
MHz
PLL locked
VPP
Differential input voltagee (peak-to-peak)
0.3
1.3
V
VCMR
Differential input crosspoint voltagef
PECL
ECL
VCC-0.3
-0.3
V
VO(P-P)
Differential output voltage (peak-to-peak)
0.8
TBD
V
frefDC
Reference Input Duty Cycle
40
60
%
t(
)
Propagation Delay (static phase offset)
ECLK, ECLK to FB_IN, FB_IN
TCLK to FB_IN, FB_IN
±150
ps
PLL locked
tsk(O)
Output-to-output Skewg
150
ps
DC
Output duty cycle
45
50
55
%
tJIT(CC)
Cycle-to-cycle jitter
RMS (1
σ)h
TBD
ps
tJIT(PER)
Period Jitter
RMS (1
σ)
TBD
ps
tJIT(
)
I/O Phase Jitter
RMS (1
σ)
TBD
ps
BW
PLL closed loop bandwidthi
kHz
tLOCK
Maximum PLL Lock Time
10
ms
tr, tf
Output Rise/Fall Time
0.05
TBD
ns
20% to 80%
a.
AC characteristics are design targets and pending characterization.
b.
AC characteristics apply for parallel output termination of 50
to VTT.
c.
In bypass mode, the MPC9991 divides the input reference clock.
d.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M VCO_SEL).
e.
VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
f.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
g.
See application section for part-to-part skew calculation.
h.
See application section for a jitter calculation for other confidence factors than 1
s.
i.
-3 dB point of PLL transfer characteristics.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
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| MPC9992ACR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992FA | 功能描述:锁相环 - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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