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参数资料
| 型号： | MPC9992FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 1/12页 |
| 文件大小： | 153K |
| 代理商： | MPC9992FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC9992
Rev 3, 05/2003
Motorola, Inc. 2004
3.3V Differential ECL/PECL
PLL Clock Generator
The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using
SiGe technology and a fully differential design ensures optimum skew and PLL
jitter performance. The performance of the MPC9992 makes the device ideal
for workstation, mainframe computer and telecommunication applications.
With output frequencies up to 400 MHz and output skews less than 100 ps the
device meets the needs of the most demanding clock applications. The
MPC9992 offers a differential PECL input and a crystal oscillator interface. All
control signals are LVCMOS compatible.
Features
7 differential outputs, PLL based clock generator
SiGe technology supports minimum output skew (max. 100 ps)
Supports up to two generated output clock frequencies with a maximum
clock frequency up to 400 MHz
Selectable crystal oscillator interface and PECL compatible clock input
SYNC pulse generation
PECL compatible differential clock inputs and outputs
Single 3.3V (PECL) supply
Ambient temperature range 0
°C to +70°C
Standard 32 lead LQFP package
Pin and function compatible to the MPC992
Functional Description
The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency
and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The
MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships.
Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be
programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range.
The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator
output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output fre-
quencies.
The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal.
The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference
clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency spec-
ification and all other PLL characteristics do not apply.
The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Asser-
tion of the reset signal forces all outputs to the logic low state.
The MPC9992 is fully 3.3V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL
compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the ca-
pability to drive terminated 50
transmission lines.
The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package.
MPC9992
3.3V DIFFERENTIAL
ECL/PECL
CLOCK GENERATOR
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
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| MPC9993D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER |
| MPC9993DFA | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER |
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