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参数资料
| 型号： | MPC9992FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 11/12页 |
| 文件大小： | 153K |
| 代理商： | MPC9992FAR2 |
MPC9992
MOTOROLA
8
TIMING SOLUTIONS
Power Supply Filtering
The MPC9992 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9992 provides separate power
supplies for the output buffers (VCC) and the phase-locked loop
(VCC_PLL) of the device. The purpose of this design technique
is to isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
illustrates a typical power supply filter scheme. The MPC9992
frequency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is the DC
voltage drop across the series filter resistor RF. From the data
sheet the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 9 mA (12 mA maximum), assuming that
a minimum of 2.955V must be maintained on the VCC_PLL pin.
10-15
to meet the voltage drop criteria.
Figure 4. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in Figure 4, the filter cut-off frequency is around 3-5 kHz
and the noise attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9992 has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Figure 5. MPC9992 AC Test Reference
VCC_PLL
VCC
MPC9992
10 nF
RF = 10 – 15
CF
33...100 nF
RF
VCC
CF = 22 F
Differential Pulse
Generator
Z = 50
RT = 50
Z = 50
RT = 50
MPC9992 DUT
VTT
Z = 50
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