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参数资料
| 型号： | MPC9992FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 6/12页 |
| 文件大小： | 153K |
| 代理商： | MPC9992FAR2 |
MPC9992
TIMING SOLUTIONS
3
MOTOROLA
Table 1. MPC9992 PLL Configurations
VCO_SEL
FSEL_0
FSEL_1
fREF (MHz)
QA[3:0] (NA)
QB[2:0] (NB)
Frequency Ratio
QA to QB
Internal Feedback
(M
VCO_SEL)
0
16.6–33.3
VCO
÷8
(6
f
REF)
VCO
÷12
(4
f
REF)
3
÷2
VCO
÷48
0
1
25–50
VCO
÷4
(8
f
REF)
VCO
÷8
(4
f
REF)
2
÷1
VCO
÷32
0
1
0
10–20
VCO
÷8
(10
f
REF)
VCO
÷20
(4
f
REF)
5
÷2
VCO
÷80
0
1
16.6–33.3
VCO
÷4
(12
f
REF)
VCO
÷12
(4
f
REF)
3
÷1
VCO
÷48
1
0
8.3–16.6
VCO
÷16
(6
f
REF)
VCO
÷24
(4
f
REF)
3
÷2
VCO
÷96
1
0
1
12.5–25
VCO
÷8
(8
f
REF)
VCO
÷16
(4
f
REF)
2
÷1
VCO
÷64
1
0
5–10
VCO
÷16
(10
f
REF)
VCO
÷40
(4
f
REF)
5
÷2
VCO
÷160
1
8.3–16.6
VCO
÷8
(12
f
REF)
VCO
÷24
(4
f
REF)
3
÷1
VCO
÷96
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
REF_SEL
1
Selects PCLK, PCLK as PLL reference signal input
Selects the crystal oscillator as PLL reference signal input
VCO_SEL
1
Selects VCO
÷2. The VCO frequency is scaled by a factor
of 2 (high input frequency range).
Selects VCO
÷4. The VCO frequency is scaled by a factor
of 4 (low input frequency range).
PLL_EN
1
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC9992 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
MR/STOP
0
Normal operation
Reset of the device and output disable (output clock stop).
The outputs are stopped in logic low state: Qx=L, Qx=H.
The minimum reset period should be greater than one
reference clock cycle.
VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 1 for the device frequency
configuration.
Table 3. Pin Configuration
Pin
I/O
Type
Function
PCLK, PCLK
Input
PECL
Differential reference clock signal input
XTAL_IN, XTAL_OUT
Analog
Crystal oscillator interface
VCO_SEL
Input
LVCMOS
VCO operating frequency select
PLL_EN
Input
LVCMOS
PLL Enable/Bypass mode select
REF_SEL
Input
LVCMOS
PLL reference signal input select
MR/STOP
Input
LVCMOS
Device reset and output clock disable (stop in logic low state)
FSEL[1:0]
Input
LVCMOS
Output and PLL feedback frequency divider select
QA[0-3], QA[0–3]
Output
PECL
Differential clock outputs (bank A)
QB[0-2], QB[0–2]
Output
PECL
Differential clock outputs (bank B)
QSYNC, QSYNC
Output
PECL
Differential clock outputs (bank C)
GND
Supply
GND
Negative power supply
VCC
Supply
VCC
Positive power supply. All VCC pins must be connected to the positive power supply for correct
DC and AC operation
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC
filter for the analog power supply pin VCC_PLL. Please see applications section for details
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