
Preliminary Product Information U14673EJ1V0PM00
66
PD789322,789324,789326,789327
Table 7-1. Operation Statuses in HALT Mode
HALT Mode Operation Status During Main
System Clock Operation
HALT Mode Operation Status During Subsystem
Clock Operation
Item
Subsystem Clock
Operating
Subsystem Clock
Stopped
Main System Clock
Operating
Main System Clock
Stopped
Main system clock
Can be oscillated
Oscillation stopped
CPU
Operation stopped
Ports (output latches)
Status before HALT mode setting retained
8-bit timer 30, 40
Operable
Operation stopped
Watch timer
Operable
Note 1
Operable
Note 2
Watchdog timer
Operable
Operation stopped
Power-on-clear circuit
Operable
Key return circuit
Operable
Serial interface 10
Operable
Note 3
LCD controller/driver
Operable
Note 4
Operable
Notes 1, 4
Operable
Note 4
Operable
Notes 2, 4
External interrupts
Operable
Note 5
Notes 1. Operation is enabled when the main system clock is selected
2. Operation is enabled when the subsystem clock is selected
3. Operation is enabled only when an external clock is selected
4. The HALT instruction can be set after display instruction execution
5. Operation is enabled only for a maskable interrupt that is not masked
Table 7-2. Operation Statuses in STOP Mode
STOP Mode Operation Status During Main System Clock Operation
Item
Subsystem Clock Operating
Subsystem Clock Stopped
Main system clock
Oscillation stopped
CPU
Operation stopped
Ports (output latches)
Status before STOP mode setting retained
8-bit timer 30, 40
Operation stopped
Watch timer
Operable
Note 1
Operation stopped
Watchdog timer
Operation stopped
Power-on-clear circuit
Operable
Key return circuit
Operable
Serial interface 10
Operable
Note 2
LCD controller/driver
Operable
Note 1
Operation stopped
External interrupts
Operable
Note 3
Notes 1. Operation is enabled when the subsystem clock is selected.
2. Operation is enabled only when an external clock is selected.
3. Operation is enabled only for a maskable interrupt that is not masked