
Preliminary Product Information U14673EJ1V0PM00
88
PD789322,789324,789326,789327
LCD Characteristics (TA =
40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VAON0
Note 1
= 1
1.8
5.5
V
LCD drive voltage
VLC0
VAON0
Note 1
= 0
2.7
5.5
V
LCD division resistance
RLCD
50
100
200
k
LCD output voltage differential
Note 2
(common)
VODC
IO =
±5
A
1/3 bias
0
±0.2
V
LCD output voltage differential
Note 2
(segment)
VODS
IO =
±1
A
1/3 bias
0
±0.2
V
Notes 1. Bit 6 of LCD display mode register 0 (LCDM0)
2. The voltage differential is the difference between the output voltage and the ideal value of the segment
and common signal outputs.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA =
40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention supply voltage
VDDDR
1.8
3.6
V
Low voltage detection (POC) voltage
VPOC
Response time: 2 ms
Note 1
1.8
1.9
2.0
V
Power supply rise time
tPth
VDD: 0 V
→ 1.8 V
0.01
100
ms
Release signal set time
tSREL
STOP cancelled by RESET
10
s
Cancelled by RESET
Note 3
s
Oscillation stabilization wait time
Note 2
tWAIT
Cancelled by interrupt request
Note 4
s
Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the
time until operation stabilizes after the shift from the operation stopped state to the operating state.
2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid
unstable operation at the start of oscillation. Program operation does not start until both the oscillation
stabilization time and the time until oscillation starts have elapsed.
3. 2
15/fX or 217/fX can be selected using the mask option (refer to 9. MASK OPTION).
4. 2
12/fX, 215/fX, or 217/fX can be selected using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization
time selection register (OSTS) (refer to 7.2 Standby Function Control Register).
Remark fX: Main system clock oscillation frequency