参数资料
型号: MR4A08BYS35R
厂商: Everspin Technologies Inc
文件页数: 8/14页
文件大小: 0K
描述: IC MRAM 16MBIT 35NS 44TSOP
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: MRAM(磁阻 RAM)
存储容量: 16M(2M x 8)
速度: 35ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 44-TSOP(0.400",10.16mm 宽)
供应商设备封装: 44-TSOP II
包装: 带卷 (TR)
Timing Specifications
Read Mode
Table 3.3 Read Cycle Timing 1
MR4A08B
Parameter
Read cycle time
Address access time
Enable access time 2
Output enable access time
Output hold from address change
Enable low to output active 3
Output enable low to output active 3
Enable high to output Hi-Z 3
Output enable high to output Hi-Z 3
Symbol
t AVAV
t AVQV
t ELQV
t GLQV
t AXQX
t ELQX
t GLQX
t EHQZ
t GHQZ
Min
35
-
-
-
3
3
0
0
0
Max
-
35
35
15
-
-
-
15
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
Addresses valid before or at the same time E goes low.
This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.
Figure 3.3A Read Cycle 1
t AVAV
A (ADDRESS)
t AXQX
Q (DATA OUT)
Previous Data Valid
Data Valid
t AVQV
Note: Device is continuously selected (E≤V IL , G≤V IL ).
Figure 3.3B Read Cycle 2
t AVAV
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
t AVQV
t ELQX
t ELQV
t EHQZ
Q (DATA OUT)
Copyright ? Everspin Technologies 2013
t GLQX
t GLQV
8
Data Valid
t GHQZ
MR4A08B Rev. 6 9/2013
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