参数资料
型号: MSC1210Y4PAGR
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 26/94页
文件大小: 913K
代理商: MSC1210Y4PAGR
MSC1210
SBAS203J MARCH 2002 REVISED JANUARY 2008
www.ti.com
32
through R7. Since there are four banks, the currently
selected bank will be used by any instruction using
R0—R7. This allows software to change context by simply
switching banks. This is controlled via the Program Status
Word register (PSW; 0D0h) in the SFR area described
below. Registers R0 and R1 also allow their contents to be
used for indirect addressing of the upper 128 bytes of
RAM. Thus, an instruction can designate the value stored
in R0 (for example) to address the upper RAM. The 16
bytes immediately above the R0—R7 registers are bit
addressable; any of the 128 bits in this area can be directly
accessed using bit addressable instructions.
FFh
7Fh
2Fh
2Dh
2Eh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
51
50
4F
4E
4D
4C
4B
4A
49
48
47
46
45
44
43
42
41
40
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
0000h
Direct
RAM
Bank 3
Bi
t
A
d
re
s
a
b
le
Bank 2
Bank 1
Bank 0
MSB
LSB
Indirect
RAM
Figure 21. Scratchpad Register Addressing
Stack
Another
use
of
the Scratchpad area is for the
programmer’s stack. This area is selected using the Stack
Pointer (SP; 81h) SFR. Whenever a call or interrupt is
invoked, the return address is placed on the Stack. It also
is available to the programmer for variables, etc., since the
Stack can be moved and there is no fixed location within
the RAM designated as Stack. The Stack Pointer will
default to 07h on reset. The user can then move it as
needed. A convenient location would be the upper RAM
area (> 7Fh) since this is only available indirectly. The SP
will point to the last used value. Therefore, the next value
placed on the Stack is put at SP + 1. Each PUSH or CALL
will increment the SP by the appropriate value. Each POP
or RET will decrement as well.
Program Memory
After reset, the CPU begins execution from Program
Memory location 0000h. The selection of where Program
Memory execution begins is made by tying the EA pin to
DVDD for internal access, or DGND for external access.
When EA is tied to DVDD, any PC fetches outside the
internal Program Memory address occur from external
memory. If
EA is tied to DGND, then all PC fetches
address external memory. The standard internal Program
Memory size for MSC1210 family members is shown in
Table 5. If enabled the Boot ROM will appear from address
F800h to FFFFh.
Table 5. MSC1210 Maximum Internal Program
Memory Sizes
PRODUCT
STANDARD INTERNAL
PROGRAM MEMORY SIZE (BYTES)
MSC1210Y5
32k
MSC1210Y4
16k
MSC1210Y3
8k
MSC1210Y2
4k
Boot ROM
There is a 2kB Boot ROM that controls operation during
serial or parallel programming. The Boot ROM routines
can be accessed during the user mode if it is enabled. The
Boot ROM routines are listed in Table 6. When enabled,
the Boot ROM routines will be located at memory
addresses F800hFFFFh during user mode. In program
mode the Boot ROM is located in the first 2kB of Program
Memory. For additional information, refer to Application
Note SBAA085, MSC1210 ROM Routines, available for
download from the TI web site (www.ti.com).
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