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参数资料
| 型号： | MT16JSF25664HY-80BXX |
| 元件分类： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, ZMA204 |
| 封装： | LEAD FREE, MO-268, SODIMM-204 |
| 文件页数： | 18/20页 |
| 文件大小： | 651K |
| 代理商： | MT16JSF25664HY-80BXX |
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
JSF16C256x64H.fm - Rev. B 6/09 EN
7
2008 Micron Technology, Inc. All rights reserved
2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
General Description
The MT16JSF25664H DDR3 SDRAM module is a high-speed, CMOS dynamic random
access 2GB memory module organized in a x64 configuration. This DDR3 SDRAM
module uses internally configured, 8-bank 1Gb DDR3 SDRAM devices.
DDR3 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially an 8n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR3 SDRAM module effectively consists of a single
8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
DDR3 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Fly-By Topology
These DDR3 modules use faster clock speeds than earlier DDR technologies, making
signal quality more important than ever. For improved signal quality, the clock, control,
command, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write leveling feature of DDR3.
Temperature Sensor with Serial Presence-Detect EEPROM
Thermal Sensor Operations
The temperature from the integrated thermal sensor is monitored and converted into a
digital word via the I2C bus. System designers can use the user-programmable registers
to create a custom temperature-sensing solution based on system requirements.
Programming and configuration details comply with JEDEC Standard No. 21-C,
page 4.7-1, “Mobile Platform Memory Module Thermal Sensor Component Specifica-
tion.”
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT16JSF25664HZ-1G1D1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX64 DDR3 SDRAM MODULE PBF SODIMM 1.5V NON BUF - Trays |
| MT16JSF25664HZ-1G1D1 TR | 制造商:Micron Technology Inc 功能描述:2GB 256MX64 DDR3 SDRAM MODULE PBF SODIMM 1.5V NON BUF - Tape and Reel |
| MT16JSF25664HZ-1G1F1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX64 DDR3 SDRAM MODULE PBF SODIMM 1.5V NON BUF - Trays |
| MT16JSF25664HZ-1G6FZES | 制造商:Micron Technology Inc 功能描述:MT16JSF25664HZ-1G6FZES - Trays |
| MT16JSF51264HZ-1G1D1 | 功能描述:MODULE DDR3 SDRAM 4GB 204SODIMM RoHS:是 类别:存储卡，模块 >> 存储器 - 模块 系列:- 标准包装:100 系列:- 存储器类型:SDRAM 存储容量:1GB 速度:133MHz 特点:- 封装/外壳:168-DIMM |
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