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参数资料
| 型号： | MT46V32M4TG-8L |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 12/68页 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-8L |
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12
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
Figure 3
Extended Mode Register Definition
EXTENDED MODE REGISTER
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable, output
drive strength, and QFC#. These functions are con-
trolled via the bits shown in Figure 3. The extended
mode register is programmed via the LOAD MODE
REGISTER command to the mode register (with
BA0 = 1 and BA1 = 0) and will retain the stored informa-
tion until it is programmed again or the device loses
power. The enabling of the DLL should always be
followed by a LOAD MODE REGISTER command to
the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
The normal full drive strength for all outputs are
specified to be SSTL2, Class II. The x16 supports an
option for reduced drive. This option is intended for
the support of the lighter load and/or point-to-point
environments. The selection of the reduced drive
strength will alter the DQs and DQSs from SSTL2, Class
II drive strength to a reduced drive strength, which is
approximately 54 percent of the SSTL2, Class II drive
strength.
The Micron 128Mb (8 Meg x16) device supports a
programmable drive strength option.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Operating Mode
Normal Operation
All other states reserved
0
–
0
–
Valid
–
0
1
DLL
Enable
Disable
DLL
11
01
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
E0
0
1
Drive Strength
Normal
Reduced
E12
0
–
QFC Function
Disabled
Reserved
E23
E0
E1,
Operating Mode
A10
A11
BA1BA0
10
11
12
13
Notes:
1. E13 and E12 (BA0 and BA1) must be
“
1, 0
”
to select the
Extended Mode Register (vs. the base Mode Register).
2. The reduced drive strength option is not supported on
the x4 and x8 versions and is only available on the D3
version of the x16 device.
3. The QFC option is not supported.
E2,
E3
E4
0
–
0
–
0
–
0
–
0
–
E6 E5
E7
E8
E9
0
–
0
–
E10
E11
DS
QFC
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