- 您现在的位置：买卖IC网 > PDF目录385639 > MT46V32M4TG-8L (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF资料下载
参数资料
| 型号： | MT46V32M4TG-8L |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 53/68页 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-8L |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
53
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
39. The voltage levels used are derived from a
minimum V
DD
level and the referenced test load.
In practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
40.
VIH overshoot: VIH(MAX) = V
DD
Q+1.5V for a
pulse width
≤
3ns and the pulse width can not
be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(MIN) = -1.5V for a pulse width
≤
3ns and the pulse width can not be greater than
1/3 of the cycle rate.
41. V
DD
and V
DDQ
must track each other.
42.
This maximum value is derived from the
referenced test load. In practice, the values
obtained in a typical terminated design may
reflect up to 310ps less for
t
HZ(MAX) and the
last DVW.
t
HZ(MAX) will prevail over
t
DQSCK(MAX) +
t
RPST(MAX) condition.
t
LZ(MIN) will prevail over
t
DQSCK(MIN) +
t
RPRE(MAX) condition.
43.
For slew rates greater than 1V/ns the (LZ)
transition will start about 310ps earlier.
44. During initialization, V
DDQ
,
V
TT
,
and V
REF
must
be equal to or less than V
DD
+ 0.3V.
Alterna-
tively, V
TT
may be 1.35V maximum during power
up, even if V
DD
/V
DDQ
are 0 volts,
provided a
minimum of 42 ohms of series resistance is used
between the V
TT
supply and the input pin.
Figure D
Pull-Up Characteristics
-120
-100
-80
-60
-40
-20
0
0.0
0.5
1.0
1.5
2.0
2.5
V
DD
Q - V
OUT
(V)
I
O
Figure C
Pull-Down Characteristics
0
10
20
30
40
50
60
70
80
0.0
0.5
1.0
1.5
2.0
2.5
V
OUT
(V)
I
O
NOTES (continued)
45. The current Micron part operates below the
slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
46.
t
RAP
≥
t
RCD.
47. For the -75 and -75Z, I
DD
3N is specified to be
35mA at 100 MHz.
48. Random addressing changing 50% of data
changing at every transfer.
49. Random addressing changing 100% of data
changing at every transfer.
50. CKE must be active (high) during the entire time
a refresh command is executed. That is, from
the time the AUTO REFRESH command is
registered, CKE must be active at each rising clock
edge, until
t
REF later.
51. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q
is similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is
“
worst case.
”
52. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V4M32 | DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M8 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
| MT46V32M82ZZ5-75EZ | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM PLASTIC 2.5V - Trays |
发布紧急采购，3分钟左右您将得到回复。