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| 型号： | MT46V32M4TG-8L |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 42/68页 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-8L |
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42
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
NOTE (continued):
3. Current state definitions:
Idle: The bank has been precharged, and
t
RP has been met.
Row Active: A row in the bank has been activated, and
t
RCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read with Auto
Precharge Enabled: See following text
–
3a
Write with Auto
Precharge Enabled: See following text
–
3a
3a. The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be
broken into two parts: the access period and the precharge period. For read with auto precharge,
the precharge period is defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still accesses all of the data in
the burst. For WRITE with auto precharge, the precharge period begins when
t
WR ends, with
t
WR
measured as if auto precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or
t
RP) begins.
During the precharge period of the READ with auto precharge enabled or WRITE with auto
precharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may
be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank
may be applied. In either case, all other related limitations apply (e.g., contention between read
data and write data must be avoided).
This means concurrent auto precharge is not supported.
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by
the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-
NATE must be used to end the READ burst prior to asserting a WRITE command.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V4M32 | DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M8 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
| MT46V32M82ZZ5-75EZ | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM PLASTIC 2.5V - Trays |
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