- 您现在的位置：买卖IC网 > PDF目录296642 > MT48LC4M32TG-10 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 PDF资料下载
参数资料
| 型号： | MT48LC4M32TG-10 |
| 元件分类： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 10/69页 |
| 文件大小： | 6213K |
| 代理商： | MT48LC4M32TG-10 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
18
2001 Micron Technology, Inc. All rights reserved.
Command Inhibit
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM,
regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO Operation (NOP)
The NO OPERATION (NOP) command is used to
instruct the selected SDRAM to perform a NOP (RAS#,
CAS#, and WE# are HIGH, CS# is LOW). This prevents
unwanted commands from being registered during
idle or wait states. Operations already in progress are
not affected.
LOAD mode register
The mode register is loaded via inputs A0–A11. Refer
to “Mode Register Definition” on page 13. The LOAD
MODE REGISTER and LOAD EXTENDED MODE REG-
ISTER commands can only be issued when all banks
are idle, and a subsequent executable command can-
not be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRE-
CHARGE command must be issued before opening a
different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A8 (x16) or A0-A7 (x32) selects the starting
column location. The value on input A10 determines
whether or not auto precharge is used. If auto pre-
charge is selected, the row being accessed will be pre-
charged at the end of the read burst; if auto precharge
is not selected, the row will remain open for subse-
quent accesses. Read data appears on the DQs subject
to the logic level on the DQM inputs two clocks earlier.
If a given DQM signal was registered HIGH, the corre-
sponding DQs will be High-Z two clocks later; if the
DQM signal was registered LOW, the DQs will provide
valid data.
WRITE
The WRITE command is used to initiate a burst
write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0-A8 (x16) or A0-A7 (x32) selects the start-
ing column location. The value on input A10 deter-
mines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto pre-
charge is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs
is written to the memory array subject to the DQM
input logic level appearing coincident with the data. If
a given DQM signal is registered LOW, the correspond-
ing data will be written to memory; if the DQM signal
is registered HIGH, the corresponding data inputs will
be ignored, and a write will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature which performs the
same individual-bank precharge function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable auto precharge
in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed
with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE
burst, except in the full-page burst mode, where auto
precharge does not apply. Auto precharge is non per-
sistent in that it is either enabled or disabled for each
individual Read or Write command.
Auto precharge ensures that the precharge is initi-
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this
data sheet.
相关PDF资料 |
PDF描述 |
|---|---|
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC4M32LFB5-10ES:G | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| MT48V4M32TG-8XT | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48LC8M8A2TG-8EL:GIT | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| MT4JSF6464HIY-80BXX | 64M X 64 DDR DRAM MODULE, ZMA204 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC4M4A1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC4M4A1TGS | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC4M4A2 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC64M4A2 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC64M4A2_03 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM 256Mb: x4, x8, x16 SDRAM |
发布紧急采购，3分钟左右您将得到回复。