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参数资料
| 型号： | MT48LC4M32TG-10 |
| 元件分类： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 26/69页 |
| 文件大小： | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
32
2001 Micron Technology, Inc. All rights reserved.
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered low.
In the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sam-
pled LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in
Figure 29 and Figure 30.)
Figure 29: Clock Suspend During WRITE
Burst
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one), regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
Figure 30: Clock Suspend During READ
Burst
DON’T CARE
DIN
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
n
NOP
CLK
T2
T1
T4
T3
T5
T0
CKE
INTERNAL
CLOCK
NOP
DIN
n + 1
DIN
n + 2
NOTE: For this example, burst length = 4 or greater, and DM
is LOW.
TRANSITIONING DATA
DON’T CA
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
MAND
DDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, a
DQM is LOW.
CKE
TERNAL
CLOCK
NOP
TRANSITIONING DATA
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