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| 型号： | MT4C4256 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 256K x 4 DRAM Standard Or Low Power, Extended Refresh(标准或低功率，扩展刷新，256K x 4动态RAM) |
| 中文描述： | 256K × 4的DRAM标准或低功耗，延长刷新（标准或低功率，扩展刷新，256K × 4动态内存） |
| 文件页数： | 7/15页 |
| 文件大小： | 240K |
| 代理商： | MT4C4256 |
MT4C4256(L)
REV. 4/94
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
1994, Micron Semiconductor, Inc.
7
MT4C4256(L)
256K x 4 DRAM
OBSOLETE
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
CC
= 5V
±
10%; f = 1 MHz.
3. I
CC
is dependent on cycle rates.
4. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100
μ
s is required after power-up
followed by any eight
/
R
A
/
S cycles before proper
device operation is assured. The eight
/
R
A
/
S cycle
wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
8. AC characteristics assume
t
T = 5ns.
9. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
11. If
/
C
A
/
S = V
IH
, data output is High-Z.
12. If
/
C
A
/
S = V
IL
, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that
t
RCD <
t
RCD (MAX). If
t
RCD is greater
than the maximum recommended value shown in this
table,
t
RAC will increase by the amount that
t
RCD
exceeds the value shown.
15. Assumes that
t
RCD
≥
t
RCD (MAX).
16. If
/
C
A
/
S is LOW at the falling edge of
/
R
A
/
S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer,
/
C
A
/
S must be
pulsed HIGH for
t
CPN.
17. Operation within the
t
RCD (MAX) limit ensures that
t
RAC (MAX) can be met.
t
RCD (MAX) is specified as
a reference point only; if
t
RCD is greater than the
specified
t
RCD (MAX) limit, then access time is
controlled exclusively by
t
CAC.
18. Operation within the
t
RAD (MAX) limit ensures that
t
RAC (MIN) and
t
CAC (MIN) can be met.
t
RAD
(MAX) is specified as a reference point only; if
t
RAD
is greater than the specified
t
RAD (MAX) limit, then
access time is controlled exclusively by
t
AA.
19. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
20.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
21.
t
WCS,
t
RWD,
t
AWD and
t
CWD are not restrictive
operating parameters.
t
WCS applies to EARLY
WRITE cycles.
t
RWD,
t
AWD and
t
CWD apply to
READ-MODIFY-WRITE cycles. If
t
WCS
≥
t
WCS
(MIN), the cycle is an EARLY WRITE cycle, and the
data output will remain an open circuit throughout
the entire cycle. If
t
RWD
≥
t
RWD (MIN),
t
AWD
≥
t
AWD (MIN) and
t
CWD
≥
t
CWD (MIN), the cycle is a
READ-MODIFY-WRITE cycle, and the data output
will contain data read from the selected cell. If neither
of the above conditions is met, the state of data-out is
indeterminate.
/
O
/
E held HIGH and
W
/
E taken LOW
after
/
C
A
/
S goes LOW results in a LATE WRITE
(
O
/
E-controlled) cycle.
t
WCS,
t
RWD,
t
CWD and
t
AWD
are not applicable in a LATE WRITE cycle.
22. These parameters are referenced to
/
C
A
/
S leading edge
in EARLY WRITE cycles and
W
/
E leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If
/
O
/
E is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case,
W
/
E = LOW and
/
O
/
E =
HIGH.
25. LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (
O
/
E HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If
O
/
E is
taken back LOW while
/
C
A
/
S remains LOW, the DQs
will remain open.
26. The DQs open during READ cycles once
t
OD or
t
OFF
occur. If
C
A
/
S goes HIGH before
O
/
E, the DQs will
open regardless of the state of
O
/
E. If
C
A
/
S stays LOW
while
O
/
E is brought HIGH, the DQs will open. If
O
/
E
is brought back LOW (
C
A
/
S still LOW), the DQs will
provide the previously read data.
27. Extended refresh current is reduced as
t
RAS is
reduced from its maximum specification during the
extended refresh cycle.
28. The 3ns minimum is a parameter guaranteed by
design.
29. Column-address changed once each cycle.
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