参数资料
型号: MT9D011D00STC
元件分类: 图像传感器
英文描述: IMAGE SENSOR-CMOS, 15fps, 0.20-0.30V
封装: DIE
文件页数: 19/64页
文件大小: 1265K
代理商: MT9D011D00STC
PDF: 81516de4(master) 8159a774(ext)/Source: 81516da4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D011__MI2010_E_2.fm - Rev. B 6/05 EN
26
2004 Micron Technology, Inc. All rights reserved.
MT9D011 - 1/3.2-Inch 2-Megapixel Digital Image Sensor
Registers
Preliminary
R13—0x0D - Reset (R/W)
Bit 15
Synchronize
Changes
By default, update of many registers are synchronized to
frame start. Setting this bit inhibits this update; register
changes remain pending until this bit is returned to “0.”
When this bit is returned to “0,” all pending register
updates are made on the next frame start.
0
N
Bit 10
Toggle SADDR
By default, the sensor serial bus responds to addresses 0xBA
and 0xBB. When this bit is set, the sensor serial bus responds
to addresses 0x90 and 0x91. Writes to this bit are ignored
when STANDBY is asserted. See “Slave Address” on page 15.
0
N
Bit 9
Restart Bad
Frames
When set, a restart is forced to take place whenever a bad
frame is detected. This can shorten the delay when waiting
for a good frame because the delay, when masking out a
bad frame, is the integration time rather than the full frame
time.
0
N
Bit 8
Show Bad
Frames
1: Output all frames (including bad frames).
0: Only output good frames (default).
A bad frame is defined as the first frame following a change
to: window size or position, horizontal blanking, pixel clock
speed, zoom, row or column skip, binning, mirroring, or use
of border.
0
N
Bit 7
Inhibit Standby By default, asserting STANDBY places the sensor in a low-
power state. Setting this bit stops STANDBY from affecting
entry to or exit from the low-power state. See See “Power-
0
N
Bit 6
Drive Pins
By default, asserting STANDBY causes the pin interface to
enter a High-Z. Setting this bit stops STANDBY from
contributing to output-enable control. See See “By applying
0
N
Bit 5
Reserved
Do not change from default value.
Bit 4
Output Disable Setting this bit puts the pin interface in a High-Z. See See
Bit 3
Reserved
Do not change from default value.
Bit 2
Standby
Setting this bit places the sensor in a low-power state.
0
N
YM
Bit 1
Restart
Setting this bit causes the sensor to truncate the current
frame and start resetting the first row. The delay before the
first valid frame is read out is equal to the integration time.
This bit is write -1 but always reads back as 0.
0
N
YM
Table 7:
Register Description (continued)
Bit Field
Description
Default
(hex)
Sync’d to
Frame Start
Bad
Frame
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