参数资料
型号: MT9D011D00STC
元件分类: 图像传感器
英文描述: IMAGE SENSOR-CMOS, 15fps, 0.20-0.30V
封装: DIE
文件页数: 6/64页
文件大小: 1265K
代理商: MT9D011D00STC
PDF: 81516de4(master) 8159a774(ext)/Source: 81516da4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D011__MI2010_E_2.fm - Rev. B 6/05 EN
14
2004 Micron Technology, Inc. All rights reserved.
MT9D011 - 1/3.2-Inch 2-Megapixel Digital Image Sensor
Two-wire Serial Register Interface
Preliminary
Two-wire Serial Register Interface
This section describes the two-wire serial interface bus that can be used in any func-
tional sensor mode.
The two-wire serial interface bus enables R/W access to control and status registers
within the MT9D011.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock
(SCLK) that is an input to the sensor and used to synchronize transfers. The master is
responsible for driving a valid logic level on SCLK at all times. Data is transferred
between the master and the slave on a bi-directional signal (SDATA). The SDATA signal is
pulled up to VDD off-chip by a 1.5kΩ resistor. Either the slave or master device can drive
the SDATA line low—the interface protocol determines which device is allowed to drive
the SDATA line at any given time.
Protocol
The two-wire serial interface bus defines the transmission codes as follows:
a start bit
the slave device 8-bit address
a(an) (no) acknowledge bit
an 8-bit message
a stop bit
Sequence
A typical read or write sequence is executed as follows:
2. The master sends a start bit.
3. The master sends the 8-bit slave device address. The last bit of the address determines
if the request is a read or a write, where a “0” indicates a write and a “1” indicates a
read.
4. The slave device acknowledges receipt of the address by sending an acknowledge bit
to the master.
5. If the request is a write, the master then transfers the 8-bit register address, indicating
where the write takes place.
6. The slave sends an acknowledge bit, indicating that the register address has been
received.
7. The master then transfers the data, eight bits at a time, with the slave sending an
acknowledge bit after each eight bits.
The MT9D011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers
to write to one register. After 16 bits are transferred, the register address is automatically
incremented so that the next 16 bits are written to the next register address. The master
stops writing by sending a start or stop bit.
A typical read sequence is executed as follows.
1. The master sends the write-mode slave address and 8-bit register address, just as in
the write request.
2. The master then sends a start bit and the read-mode slave address, and clocks out the
register data, eight bits at a time.
3. The master sends an acknowledge bit after each 8-bit transfer. The register address is
auto-incremented after every 16 bits is transferred.
4. The data transfer is stopped when the master sends a no-acknowledge bit.
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