参数资料
型号: MT9D011D00STC
元件分类: 图像传感器
英文描述: IMAGE SENSOR-CMOS, 15fps, 0.20-0.30V
封装: DIE
文件页数: 49/64页
文件大小: 1265K
代理商: MT9D011D00STC
PDF: 81516de4(master) 8159a774(ext)/Source: 81516da4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D011__MI2010_E_2.fm - Rev. B 6/05 EN
53
2004 Micron Technology, Inc. All rights reserved.
MT9D011 - 1/3.2-Inch 2-Megapixel Digital Image Sensor
Feature Description
Preliminary
The falling edge of FLASH cannot be programmed to occur before the rising edge.
The FLASH pin will always be de-asserted when readout starts (even if the falling edge
is programmed to occur after start of readout).
To avoid an extra pulse on the FLASH pin when readout of the global reset frame starts,
it is a requirement that if the FLASH pulse in ERS mode is enabled, the programming of
it through Reg0x23 should be done such that the "ERS" FLASH pulse is over before the
readout of the global frame starts.
When the integration time (and the start of readout) is controlled externally by the
GRST_CTRL pin, the FLASH pin should not be used during global reset, and Reg0xC5 -
Reg0xC6 should be set to zero.
Anti-Eclipse
When a very bright object such as the sun is present in the image, it is possible for a dark
spot to appear in the center of the object. This is the so-called “eclipse” effect. The dark
spot can be removed by setting Reg0x38 to 0x0826.
Analog Signal Path
The MT9D011 features two identical analog readout channels. A block diagram for one
channel is shown in Figure 31. The readout channel consists of two gain stages (ASC1
and ASC2), a sample-and-hold (ADCSH) stage with black level calibration capability
(VOFFSET), and a 10-bit ADC.
Figure 31: Analog Readout Channel
Stage-by-Stage Transfer Functions
Transfer functions proceed stage-by-stage, as follows:
Let VPIX be the input of the signal path:
VPIX = pixel output voltage = signal path input voltage,
The output voltage of ASC 1st stage is:
V1 = -1*G1*VPIX
(1)
The output voltage of ASC 2nd stage is:
V2 = -1*G2*V1
(2)
The output voltage of ADC Sample-and-Hold stage is:
V3 = 2*G3*V2 - VREFD + VOFFSET
(3)
and the ADC output code is:
ADC output code = 511*(1 + (V3 / VrEFD))
(4)
From (1) to (4), the ADC output code can also be written as: ADC code = (1022/VREFD)*[G1*G2*G3*VPIX +
(Voffset/(2*G3))]
(5)
ASC1
ASC2
ADCSH
10-bit
(G1)
(G2)
(G3)
ADC
V1
V2
V3
Vpix
ADC_code
10
VOFFSET
VREFD
+
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