参数资料
| 型号： | NB4N441MNGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/18页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NB4N441MNG |
| 标准包装： | 1 |
| 系列： | * |
NB4N441MNGEVB
LAMINATION STACK
L1
L2
L3
L4
Signal
SMAGND
V CC and DUTGND
DUTGND and Signal
LAMINATION DIAGRAM
Layer
Number
1
Layer
Name
TOP
Copper
Thickness
1/2 OZ.
Dielectric
Thickness
Layer
Material
Trace
Width
0.012
0.006
GETEK
2
3
4
SMAGND
PWR
DUTGND
1 OZ.
1 OZ.
1/2 OZ.
Adjust
0.006
GETEK
GETEK
???
???
0.011
FINISHED PCB THICKNESS TO BE:
0.64 ± 0.003
ASSEMBLY NOTES:
Notes (Unless Otherwise Specified)
Material:
1. GETEK Laminate Epoxy/Polyphenylene Oxide
Resin Type NEMA FR ? 4 (IPC ? L ? 1088/04). See
Layer Table. Inner Layers: 1 oz. Copper clad
Outer Layers: 1/2 oz. Copper Foil Plated to 1
1/2 oz finished.
2. Refer to Stacking Diagram for Finished Board
Thickness.
Tooling:
3. Photo etch circuitry per artwork drill locations
controlled by drill file.drl fabrication print.
4. The dielectric thickness of the controlled
impedance layers is for reference only. Final
acceptance shall be determined by these layer pairs
having a characteristic impedance of 52.5 W
$ 10%. The vendor can make width adjustments
on only the critical conductor widths of $ 0.0005.
All other adjustments must have prior approval
from Baldwin Tech Layer Grouping (1.2).
5. Finished conductor width to be 0.012”.
Finish:
6. Plating Specification: Electrodeposited hard gold
plate, Type 1 (99.7% min gold) Grade C (Knoop
Hardness 130 ? 200), Class 1 (50 ? 100 micro ? inches
thick) in accordance with MIL ? G ? 4520C and
ANSI/IPC ? A ? 6000. Section 4.0 (surface placing
acceptability requirements), Class 3 (50 ? 100
micro ? inches thick) over electrodeposited nickel
plate in accordance with ANSI/IPC ? A ? 6000,
Section 4.0, Class 3 (200 ? 600 micro ? inches thick).
7. Drill sizes are finished. Plated through holes to
have a minimum barrel plating of 0.0008 in.
8. Board twist and warp not to exceed 0.005 in (5%)
per linear inch. Front to back registration to be
within 0.003 in.
9. True position tolerance shall be determined by a
minimum anular ring of 0.005 in.
10. Plated holes shall not be rough or irregular so as to
hinder proper solder wicking.
11. Soldermask: Green LPI: B0
12. Apply Legend (SILKSCREEN) to both sides using
a nonconductive, white, Epoxy based ink per
artwork.
13. No board shop logo on board.
14. Each PCB shall be serialized, in legend, in the area
shown, as follow: 0005 ? 1 ? 1 (Sequential Number
(assigned per panel) ? Panel Number (assigned per
log) ? Year and Week).
Testing:
15. Final Electrical Test shall be preformed per
provided IPC ? 356 netlist. The PCB shall have a
verification stamp. Connectivity to be verified
against IPC format net list.
16. A TDR report for each layer shall be provided by
vendor at time of shipment.
http://onsemi.com
17
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