参数资料
| 型号： | NB4N441MNGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NB4N441MNG |
| 标准包装： | 1 |
| 系列： | * |
NB4N441MNGEVB
APPENDIX 1: DEVICE AND BOARD INFORMATION
SEE CURRENT DATASHEET
DEVICE PINS:
Pin Name
Open Pin
Pin #
1
441
GND
I/O
Supply
Default
Type
Negative Power Supply (Ground)
Function
2
NC
No Connect
3
4
5
6
7
8
9
10
11
12
13
14
VCCPLL
NC
NC
GND
XTAL2
CLK/XTAL1
GND
NC
VCC
VCC
VCC
NC
Supply
Supply
Input
Input
Supply
Supply
Supply
Supply
Positive supply for the PLL and is connected to +3.3 V
No Connect
No Connect
Negative Power Supply (Ground)
Crystal Oscillator Interface ? Crystal Input
CMOS/TTL Crystal Oscillator Interface ? Crystal Input or External Clock Input
Negative Power Supply (Ground)
No Connect
Positive Power Supply
Positive Power Supply
Positive Power Supply
No Connect
15
16
17
18
19
20
21
SLOAD
SDATA
SCLOCK
GND
GND
LOCKED
OE
Input
Input
Input
Supply
Supply
Output
Input
L
L
L
H
CMOS/TTL Serial Load Input
CMOS/TTL Serial Data Input
CMOS/TTL Serial Clock Input
Negative Power Supply (Ground)
Negative Power Supply (Ground)
CMOS/TTL PLL Locked Indicator
CMOS/TTL Synchronous Output Enable. Active HIGH. The Enable is synchronous to the
output clock to eliminate the possibility of runt pulses on the CLKOUT
outputs.
22
23
24
CLKOUT
CLKOUT
VCC
Output
Output
Supply
LVPECL
LVPECL
Differential Clock Output
Differential Clock Output
Positive Power Supply
Board Pins
Input Clock: An SMA connector (J1) board trace to
CLK/XTAL1 device pin contains a gap placed on the board
trace at the crystal pin (J5). This board trace and connector
are open and not connected to the crystal pin and has no
impedance affect on the crystal pin. A short must bridge this
gap to connect the INPUT CLOCK SMA to the device
CLK/XTAL1 pin. A 50 W termination resistor may be added
from the board trace from CLK to SMAGND at the SMA
connector, or, install a 50 W resistor in place of C6.
SW4, 6 and 7 are the M, N, and P SELECT: DIP switches
JP1 is an LED power supply jumper provided to disable the
LED’s and their current. Disabling the LEDs will allow
measuring only the device power supply current.
Output CLOCK and Output CLOCK : The outputs
have equal length board traces with SMA connectors, J2 &
J4. Use matched cables to connect the outputs to an
Serial Pins (NB4N441) SCLOCK, SDATA and
SLOAD pins have board traces connected to SMA
connectors J10, J9 and J7 for external control. There are no
50 W termination resistors on these nodes. If signal sources
requiring output termination are needed to drive SCLOCK,
SDATA and SLOAD, a 50 W resistor can be added, from the
board trace at the SMA conductor to SMA ground.
Output Enable : The Output Enable function is carried
out manually with the switch, SW1, or externally via SMA
connector J11, and observing the OUTPUT CLOCK &
OUTPUT CLOCK CLKOUT pins.
PLL LOCKED There are two convenient PLL indicator
LEDs, green for when the device is PLL LOCKED and red
for PLL not LOCKED.
LED/PLD Power : The LED and PLD power can be
disabled by leaving JP1 open or removing shunt from JP1.
oscilloscope or frequency counter. Alternative connection
pads are supplied for installation of a Thevenin termination
scheme.
http://onsemi.com
6
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| NB4N441MNR2G | 功能描述:锁相环 - PLL MLTPRTCL PLL CLK SYN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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