参数资料
| 型号： | NB4N441MNGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NB4N441MNG |
| 标准包装： | 1 |
| 系列： | * |
NB4N441MNGEVB
TEST AND MEASUREMENT SETUP AND PROCEDURE
Step 1: Equipment (or equivalent)
1. Agilent Signal Generator #33250A for CLK input
2. Tektronix TDS8000 Oscilloscope or Frequency
Counter
3. Agilent #6624A DC Power Supply
4. Digital Voltmeter
5. Matched high ? speed cables with SMA connectors
Step 2: Lab Setup Procedure for Split Supplies (into
LOW impedance 50 W equipment or probes)
1. Output Enable OFF : Switch SW1 (UP) or
externally LOW through J11 (offset LVCMOS/
LVTTL of 2.0 V HIGH and ? 1.3 V LOW) to
disable the output during setup. LED D3 indicator
will be off to indicate disabled output.
2. Supplies : Connect a “split” power supply to the
evaluation board for 3.3 V operation as follows:
V CC (RED banana jack or clip anvil) at +2.0 V
SMAGND (YELLOW banana jack or clip
anvil) at 0 V
DUTGND (BLACK banana jack or clip anvil)
? 1.3 V
3. Output : Connect LVPECL Output CLOCK and
Output CLOCK outputs to the oscilloscope with
matched cables.
NOTE: The readings of the output voltage levels
will be offset by ? 1.3 V from standard LVPECL
levels. With this split supply, the device outputs
will be parallel terminated by the oscilloscope (or
frequency counter) input module’s internal 50 W to
GND impedance. See the data sheet Figure 10,
where SMAGND = V TT = V CC ? 2.0 V = 0 V=
OSCILLOSCOPE GND.
An alternative thevenin parallel termination
scheme can been accommodated by using the
unpopulated Resistor Pads (R76, R77, R78, and
R79) provided on the OUTPUT CLOCK and
OUTPUT CLOCK lines near the SMA connectors.
See AND8020 for additional details. Do not use
both thevenin parallel termination scheme and
LOW IMPEDANCE (50 W ) termination schemes
on the same output at the same time (double
termination).
4. Trigger : Ensure the oscilloscope trigger input is
properly setup and adjusted and has a 50 W
termination to ground. The board does not provide
50 W source termination resistors. Two possible
oscilloscope trigger methods might be
1. “T” connector from CLKOUT to the trigger of the
scope,
2. Use CLKOUT directly to the trigger.
3. XTAL/CLK Input: Determine if the onboard
crystal or an external signal reference will be used.
Onboard Crystal signal source (27 MHz) is default
ready for use.
NOTE: If an external clock reference is used, then
dismount the crystal and connect a clock signal
(10 MHz ? 50 MHz, 3.3 V PP amplitude) with
LEVELS OFFSET ? 1.3 V: as +2.0 V HIGH and
? 1.3 V LOW into CLK/XTAL1 (J1). Also short
from the bottom side “through hole trace” of
INPUT CLOCK to J5 (not J3). Do not drive
XTAL2. Termination of the signal generator may
be needed with 50 W to SMA ground.
4. Program SDI: The P, M, and N internal registers
may be programmed by (A) the onboard PLD or
(B) by using the three line 3.3 V PP amplitude
(offset LVTTL/LVCMOS) Serial Data Interface
(SDI) consisting of a SERIAL DATA (SDATA)
input, a SERIAL CLOCK (SCLOCK) input, and a
SERIAL LOAD (SLOAD) as follows:
A. Onboard PLD
1. Insure all 4 of the J12 (441 CONFIG) jumpers
are all installed connecting the PLD output to
the Device
2. Insure JP1 LED/PLD indicates power is
applied to the PLD (LED on);
3. Insure J3 (external CLOCK line from J1) is
open, not LOADED, DRIVEN, or shorted;
4. Insure SW5 (LEFT: CUSTOM 441,
RIGHT:STANDARD 442) select is set to the
LEFT (bypassing SW2, SEL[3:0]. Note LED
will light for “CUSTOM FREQUENCIES”.
5. Set SW4, SW6, and SW7 rocker switches to
desired P, M, and N programming values:
UP =0 LOGIC LOW (LED indicator OFF);
DOWN = 1 LOGIC HIGH (LED indicator
ON).
6. Load program values by depressing
momentary switch SW8, or send a pulse
signal (125 ns min) through J13 SMA
connector (when installed) with OFFSET
LVCMOS/LVTTL LEVELS of +2.0 V HIGH
and ? 1.3 V LOW.
B. External SDI
1. See datasheet DC Table, AC Table, as well as
Figures 5 and 6.
2. To use the SDI (serial data input) port,
generate and input SCLOCK, SDATA, and
SLOAD signals with OFFSET
LVCMOS/LVTTL LEVELS of +2.0 V HIGH
and ? 1.3 V LOW. The SCLOCK signal will
sample the information presented on SDATA
line. Values are loaded and indexed into a 18
bit shift register. The register shifts once per
rising edge of the SCLOCK input. The serial
input SDATA bits must each meet setup and
http://onsemi.com
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