参数资料
| 型号： | NCP1034DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/23页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 80% |
| 电源电压： | 10 V ~ 18 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1118 (CN2011-ZH PDF) |
| 其它名称： | NCP1034DR2GOSDKR |
NCP1034
Undervoltage Lock ? out
There are four undervoltage lock ? out circuits. Two of
them protect external high ? side and low ? side drivers, the
third ensures that the IC does not start until V CC is under a
set threshold. The last one can be programmed by the user.
It has a rising threshold at 1.25 V and a falling threshold at
1.15 V, and the user can define the undervoltage level by an
external resistor divider. If the voltage is not over the
threshold value, the device stops operating. The high ? side
driver UVLO only stops switching the high ? side MOSFET
Programmed falling and rising UVLO voltage can be
calculated by Equations 1 and 2:
500
450
400
350
300
250
200
150
100
50
and
V UVLO,falling + 1.15 @ 1 )
R4
R5
(eq. 1)
0
0
50 100 150 200 250
R t (k W )
Figure 20. Frequency Dependence of R t Value
V UVLO,rising + 1.25 @ 1 )
R4
R5
(eq. 2)
Frequency Synchronization
Shutdown
The output voltage can be disabled by pulling the
SS/SD pin below 0.3 V. A small transistor can be used to pull
it down as shown in Figure 19. During this time, both
external MOSFETs are turned off. After the SS/SD pin is
released, the IC starts its operation with a soft ? start
sequence.
The NCP1034 can be synchronized to an external clock
signal. The input synchronization signal should be a TTL
logic level. The oscillator is synchronized to the rising edge
of the synchronizing signal. When synchronization is used,
the free running frequency must be set by the timing resistor
to a frequency at least 80% of the external synchronization
frequency (Example: R T = 20 k W / 200 kHz and external
TTL = 220 kHz).
SS/SD
Figure 19. Shutdown Interface
Operating Frequency Selection
SS/SD
The NCP1034 can also output synchronization pulses on
the SYNC pin. Pulses are generated when the internal
oscillator ramp reaches the high threshold voltage. The
frequency of these pulses is set by an external R T resistor. Up
to five NCP1034 controllers can be connected directly to the
SYNC pin, all of which are synchronized to the controller
with the highest frequency. The lowest frequency must be at
least 80% of the highest one.
The equivalent internal circuit of the Sync pin is shown in
Figure 21.
V BIAS
The operating frequency is set by an external resistor
connected from the R t Pin to ground. The value of this
resistor can be selected from Figure 20, which shows
switching frequency versus the timing resistor value.
SYNC
R t
R t
Oscillator
C t
Figure 21. Equivalent Connection of the Sync Pin
http://onsemi.com
11
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