参数资料
| 型号： | NCP1034DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/23页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 80% |
| 电源电压： | 10 V ~ 18 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1118 (CN2011-ZH PDF) |
| 其它名称： | NCP1034DR2GOSDKR |
NCP1034
Figure 22 shows the part with no synchronization. In this
circuit the internal clock is fixed by the external timing
resistor R T . The SYNC pin can be tied to GND through a
series resistor to prevent false triggering in a noisy
environment.
SYNC
SYNC
NCP1034
(Master #1)
R T
F SW = 200 kHz
20 k W
SYNC
NCP1034
(Slave #1)
R T
F SW = 180 kHz
22 k W
10 k W
(optional)
NCP1034
SYNC
NCP1034
(Slave #2)
20 k W
R T
Synchronized System
Frequency = 200 kHz
R T
F SW = 180 kHz
V OUT + V ref @ 1 )
R1
F SW = 200 kHz
Figure 22. Fixed Frequency
Figure 23 shows the part synchronized to an external
clock through the SYNC pin. The synchronization
frequency can be up to 20% greater then the programmed
fixed frequency (Example: R T = 20 k W / 200 kHz and the
SYNC input frequency can range from 200 ? 220 kHz). The
clock frequency at the SYNC pin replaces the master clock
generated by the internal oscillator circuit. Pulling the
SYNC pin low programs the part to run freely at the
frequency programmed by R T . When pulling the SYNC pin
low a 4.7 k Ω resistor should be used.
22 k W
Figure 24. Master Slave Synchronization
Output Voltage
Output voltage can be set by an external resistor divider
according to this Equation 3:
(eq. 3)
R2
Where V ref is the internal reference voltage 1.25 V. Absolute
values of resistors R1 and R2 depend on compensation
network type. See compensation paragraph for details.
TTL
Logic
4.7 k W
(optional)
Input: = 220 kHz
20 k W
SYNC
NCP1034
R T
F SW = 220 kHz
Inductor Selection
The inductor selection is based on the output power,
frequency, input and output voltage and efficiency
requirements. High inductor values cause low current
ripple, slower transient response, higher efficiency and
increased size. Inductor design can be reduced to desire
maximum current ripple in the inductor. It is good to have
current ripple ( D I Lmax ) between 20% and 50% of the output
current.
For buck converter, the inductor should be chosen
according to Equation 4.
Figure 23. External Synchronization
Figure 24 shows the part operating in the master slave
L +
V OUT
f @ D I Lmax
1 *
V OUT
V INmax
(eq. 4)
synchronization configuration. In this configuration all
three parts are connected together through the SYNC pin in
order to synchronize the system switching frequency. The
R T timing resistor can be the same value for all three parts
(R T = 20 k W / 20 k W / 20 k W ) which would make the highest
frequency part the master, or to guarantee one part is the
master the timing resistor can be slightly lower in value. (R T
= 20 k W / 22 k W / 22 k W )
Output Capacitor Selection
The output voltage ripple and transient requirements
determine the output capacitor type and value. The
important parameter for the selection of the output capacitor
is equivalent serial resistance (ESR). If the capacitor has low
ESR, it often has sufficient capacity for filtering as well as
an adequate RMS current rating.
http://onsemi.com
12
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