参数资料
| 型号： | NCP1034DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 80% |
| 电源电压： | 10 V ~ 18 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1118 (CN2011-ZH PDF) |
| 其它名称： | NCP1034DR2GOSDKR |
NCP1034
High ? Side
Logic Signal
Low ? Side
Logic Signal
R DSmax
High ? Side
MOSFET
t d(on)
t dead
t f
t dead
R DS(on)min
R DSmax
Low ? Side
MOSFET
t r
t d(off)
t r
t f
R DS(on)min
t d(on)
t d(off)
Figure 25. MOSFETs Timing Diagram
t d(on)high ) t dead u t d(off)low ) t f low
MOSFETs delays, turn ? on and turn ? off times must be
short enough to prevent cross conduction. If not, there will
be cross conduction from the input through both MOSFETs
to ground. Due to this fact, the following conditions must be
true:
(eq. 14)
t d(on)low ) t dead u t d(off)high ) t f high
Where t dead is the controller dead band time, t d(on) , t r , t d(off)
and t f are MOSFETs parameters. These parameters can be
found in the datasheet for specific conditions.
Bootstrap Circuit
This circuit is used to obtain a voltage higher than the
input voltage in order to switch ? on high side N MOSFET.
The bootstrap capacitor is charged from the IC’s supply
voltage through D1, when the low side MOSFET is
switched ? on up to the IC’s supply voltage. It must have
enough capacity to supply power for the high ? side circuit
when the high ? side MOSFET is being switched on. The
minimum value recommended for the bootstrap capacitor is
100 nF. Diode D1 has to be designed to withstand a reverse
voltage given by the following equation:
D1 VRmin + V IN * V CC (eq. 15)
Soft ? Start
The soft ? start time is set by capacitor connected between
SS/SD Pin and ground. This function is used for controlling
the output voltage slope and limiting startup currents. The
supply voltage, low side drive supply voltage and external
UVLO are over the set thresholds. The soft ? start capacitor
is charged by 20 m A current source. If POR is low, the SS/SD
Pin is internally pulled to GND, which means that the
NCP1034 is in a shutdown state. The SS/SD Pin voltage
(0 V to 2.6 V) controls internal current source (64 m A to
0 m A) with negative linear characteristic. This current
source injects current into the resistor (25 k W ) connected
between the Fb pin and negative input of the error amplifier
and into the external feedback resistor network. Voltage
drop on these resistors is over 1.6 V, which is enough to force
the error amplifier into negative saturation state and to block
switching.
When the soft ? start pin reaches around 1.2 V (exact value
depends on feedback and compensation network and on
soft ? start capacitor; a larger soft ? start capacitor and a lower
compensation capacity decrease this level) the IC starts
switching. The impact of controlled current source
decreases and the output voltage starts to rise. When the
soft ? start capacitor voltage reaches 2.6 V, the output voltage
is at nominal value.
The soft ? start time must be at least 10 times longer than
the time needed to charge the compensation network from
the output of the error amplifier. If the soft ? start time is not
long enough, the soft ? start sequence would be faster than the
charging compensation network and the IC would start
without slowly increasing the output voltage. The soft ? start
capacitance can be calculated using Equation 16.
start ? up sequence initiates when Power On Ready (POR)
internal signal rises to logic high level. That means the
http://onsemi.com
14
C SS + 15 @ 10 ? 6 @ T SS
(eq. 16)
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