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参数资料
| 型号： | NCP1252BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO PWM 8SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 84% |
| 电源电压： | 9 V ~ 28 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -25°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP1252
V BO V bulkon * V BO
R BOlo + * 1
I BO
V bulkoff * V BO
R BOup +
V bulkon * V bulkoff
I BO
R BOlo + 1 370 * 1 * 1 + 5731 W
R BOup + 370 * 350 + 2.0 M W
(eq. 4)
R BOup can be also written independently of R BOlo by
substituting Equation 4 into Equation 3 as follow:
(eq. 5)
From Equation 4 and Equation 5, the resistor divider value
can be calculated:
10 m 350 * 1
10 m
Short Circuit or Over Load Protection:
A short circuit or an overload situation is detected when
the CS pin level reaching its maximum level at 1 V. In that
case the fault status is stored in the latch and allows the
digital timer count. If the digital timer ends then the fault is
latched and the controller permanently stops the pulses on
the driver pin.
If the fault is gone before ending the digital timer, the
timer is reset only after 3 switching controller periods
without fault detection (or when the CS pin < 1 V during at
least 3 switching periods).
If the fault is latched the controller can be reset if a BO
reset is sensed or if V CC is cycled down to V CC(off) .
Fault timer: 15 ms
CS pin
(500 mV/div)
12 Vout
Short Circuit
(5 V/div)
Time
(4 ms/div)
Figure 35. Short Circuit Detection Example
Shut Down
There is one possibility to shut down the controller; this
possibility consists at grounding the BO pin as illustrated in
Figure 34.
Ramp Compensation
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half of the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty ? cycle
close to and above 50%. To lower the current loop gain, one
usually injects between 50 and 100% of the inductor
downslope. depicts how internally the ramp is generated:
The ramp compensation applied on CS pin is from the
internal oscillator ramp buffered. A switch placed between
the buffered internal oscillator ramp and R ramp disconnects
the ramp compensation during the OFF time DRV signal.
http://onsemi.com
14
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