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参数资料
| 型号： | NCP1252BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO PWM 8SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 占空比： | 84% |
| 电源电压： | 9 V ~ 28 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -25°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP1252
Table 3. ELECTRICAL CHARATERISTICS
(V CC = 15 V, R T = 43 k W , C DRV = 1 nF. For typical values T J = 25 ° C, for min/max values T J = –25 ° C t o +125 ° C , unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION AND V CC MANAGEMENT
Startup threshold at which driving pulses are au-
thorized
Minimum Operating voltage at which driving pulses
are stopped
Hysteresis between V CC(on) and V CC(min)
Start ? up current, controller disabled
Internal IC consumption, controller switching
Internal IC consumption, controller switching
V CC increasing
V CC decreasing
V CC < V CC(on) & V CC increasing
from zero
F sw =100 kHz, DRV = open
F sw =100 kHz, C DRV = 1 nF
V CC(on)
V CC(off)
V CC(HYS)
I CC1
I CC2
I CC3
9.4
8.4
0.9
?
0.5
2.0
10
9
1.0
?
1.4
2.7
10.6
9.6
?
100
2.2
3.5
V
V
V
m A
mA
mA
CURRENT COMPARATOR
Current Sense Voltage Threshold
Leading Edge Blanking Duration
V ILIM
t LEB
0.92
?
1
160
1.08
?
V
ns
Input Bias Current
Propagation delay
Internal Ramp Compensation Voltage level
Internal Ramp Compensation resistance to CS pin
(Note 3)
From CS detected to gate
turned off
@ 25 ° C (Note 4)
@ 25 ° C (Note 4)
I bias
t ILIM
V ramp
R ramp
?
?
3.15
?
0.02
70
3.5
26.5
?
150
3.85
?
m A
ns
V
k W
INTERNAL OSCILLATOR
Oscillator Frequency
Oscillator Frequency
Frequency Modulation in percentage of f OSC
Frequency modulation Period
Maximum operating frequency
Maximum duty ? cycle – A version
Maximum duty ? cycle – B version
Maximum duty ? cycle – C version
R T = 43 k W & DRV pin = 47 k W
R T = 8.5 k W & DRV pin = 47 k W
(Note 3)
(Note 3)
(Note 3)
f OSC
f OSC
f jitter
T swing
f MAX
DC maxA
DC maxB
DC maxC
92
425
?
?
500
45.6
76
61
100
500
± 5
3.33
?
48
80
65
108
550
?
?
?
49.6
84
69
kHz
kHz
%
ms
kHz
%
%
%
FEEDBACK SECTION
Internal voltage division from FB to CS setpoint
Internal pull ? up resistor
FB div
R pull ? up
?
?
3
3.5
?
?
?
k W
FB pin maximum current
Internal feedback impedance from FB to GND
Open loop feedback voltage
Internal Diode forward voltage
FB pin = GND
FB pin = open
(Note 3)
I FB
Z FB
V FBOL
V f
1.5
?
?
?
?
40
6.0
0.75
?
?
?
?
mA
k W
V
V
DRIVE OUTPUT
DRV Source resistance
DRV Sink resistance
R SRC
R SINK
?
?
10
6
30
19
W
W
Output voltage rise ? time
Output voltage fall ? time
V CC = 15 V, C DRV = 1nF,
10 to 90%
V CC = 15 V, C DRV = 1nF,
90 to 10%
t r
t f
?
?
26
22
?
?
ns
ns
3. Guaranteed by design
4. V ramp , R ramp Guaranteed by design
http://onsemi.com
4
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