参数资料
型号: NCP3101BUCK2GEVB
厂商: ON Semiconductor
文件页数: 10/26页
文件大小: 0K
描述: EVAL BOARD FOR NCP3101BUCK2G
设计资源: NCP3101BUCK2 EVB BOM
NCP3101BUCK2GEVB Gerber Files
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.5V
电流 - 输出: 6A
输入电压: 5V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP3101
其它名称: NCP3101BUCK2GEVBOS
NCP3101C
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal soft start, SS, is
discharged, and all gate pins go low. The switch node enters
a high impedance state and the output capacitors discharge
through the load with no ringing on the output voltage.
External Soft ? Start
The NCP3101C features an external soft start function,
which reduces inrush current and overshoot of the output
VCC
COMP
VFB
BG
4.3 V
0.9 V
3.4 V
voltage. Soft start is achieved by using the internal current
source of 10 m A (typ), which charges the external integrator
capacitor of the transconductance amplifier. Figures 22
and 23 are typical soft start sequences. The sequence begins
once V CC surpasses its UVLO threshold. During Soft Start
as the Comp Pin rises through 400 mV, the PWM logic and
TG
BG Comparator
DAC Voltage
BG Comparator
Output
50mV
500mV
gate drives are enabled. When the feedback voltage crosses
POR Trip Set
Delay
800 mV, the EOTA will be given control to switch to its
higher regulation mode with the ability to source and sink
130 m A. In the event of an over current during the soft start,
the overcurrent logic will override the soft start sequence
Vout
UVLO
Current Normal Operation
COMP
Delay
Figure 23. Soft ? Start Sequence
UVLO
and will shut down the PWM logic and both the high side and
low side gates of the switching MOSFETS.
0.83V
UVLO
Under Voltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when V CC is too low to
support the internal rails and power the converter. For the
Vcomp
0.4V
0.4V
NCP3101C, the UVLO is set to ensure that the IC will start
up when VCC reaches 4.0 V and shutdown when V CC drops
below 3.6 V. The UVLO feature permits smooth operation
Enable
0.8V
from a varying 5.0 V input source.
Current Limit Protection
In case of a short circuit or overload, the low ? side (LS)
Vfb
Isource/
sink
10uA
SS
120uA
10uA
FET will conduct large currents. The low ? side R DS(on) sense
is implemented to protect from over current by comparing
the voltage at the phase node to AGND just prior to the low
side MOSFET turnoff to an internally generated fixed
Normal
? 10uA
Start up
Figure 22. Soft ? Start Implementation
voltage. If the differential phase node voltage is lower than
OC trip voltage, an overcurrent condition occurs and a
counter is initiated. If seven consecutive over current trips
are counted, the PWM logic and both HS ? FET and LS ? FET
are turned off. The converter will be latched off until input
power drops below the UVLO threshold. The operation of
key nodes are displayed in Figure 24 for both normal
operation and during over current conditions.
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