参数资料
型号: NCP3101BUCK2GEVB
厂商: ON Semiconductor
文件页数: 17/26页
文件大小: 0K
描述: EVAL BOARD FOR NCP3101BUCK2G
设计资源: NCP3101BUCK2 EVB BOM
NCP3101BUCK2GEVB Gerber Files
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.5V
电流 - 输出: 6A
输入电压: 5V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP3101
其它名称: NCP3101BUCK2GEVBOS
NCP3101C
F ESR +
3
16.2 kHz +
3
MOSFET turning off and the high ? side
MOSFET turning on, typically 42 ns
P BODY = Low ? side MOSFET body diode losses
V FD = Body diode forward voltage drop
Control Dissipation
The control portion of the IC power dissipation is
determined by the formula below:
P C + I CC * V CC (eq. 34)
I CC = Control circuitry current draw
P C = Control power dissipation
V CC = Input voltage
Once the IC power dissipations are determined, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient temperature. The formula for calculating the
1
2 p * CO ESR * C OUT
(eq. 37)
1
2 p * 12 m W * 820 m F
CO ESR = Output capacitor ESR
C OUT = Output capacitor
F LC = Output capacitor ESR frequency
The two equations above define the bode plot that the
power stage has created or open loop response of the system.
The next step is to close the loop by considering the feedback
values. The closed loop crossover frequency should be
greater then the F LC and less than 1/5 of the switching
frequency, which would place the maximum crossover
frequency at 55 kHz. Further, the calculated F ESR frequency
should meet the following:
T J + T A ) P D @ R q JC
junction temperature with the package in free air is:
(eq. 35)
F ESR +t
F SW
5
(eq. 38)
P D = Power dissipation of the IC
R q JC = Thermal resistance junction ? to ? case of
the regulator package
T A = Ambient temperature
T J = Junction temperature
As with any power design, proper laboratory testing
should be performed to ensure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
F SW = Switching frequency
F ESR = Output capacitor ESR zero frequency
If the criteria is not met, the compensation network may
not provide stability, and the output power stage must be
modified.
Figure 29 shows a pseudo Type III transconductance error
amplifier.
ZIN
maximum input voltage, maximum loading, and component
variations (i.e., worst case MOSFET R DS(on) ).
Compensation Network
IEA
R1
CF
RF
To create a stable power supply, the compensation
network around the transconductance amplifier must be
used in conjunction with the PWM generator and the power
CC
ZFB
CP
Gm
R2
stage. Since the power stage design criteria is set by the
application, the compensation network must correct the
overall output to ensure stability. The output inductor and
capacitor of the power stage form a double pole at the
frequency shown in Equation 36:
RC
VREF
F LC +
3
2.35 kHz +
C OUT
F LC
L OUT
1
2 p * L OUT * C OUT
(eq. 36)
1
2 p * 5.6 m H * 820 m F
= Output capacitor
= Double pole inductor and capacitor
frequency
= Output inductor value
Figure 29. Pseudo Type III Transconductance Error
Amplifier
The compensation network consists of the internal error
amplifier and the impedance networks Z IN (R 1 , R 2 , R F , and
C F ) and external Z FB (R C , C C , and C P ). The compensation
network has to provide a closed loop transfer function with
the highest 0 dB crossing frequency to have fast response
and the highest gain in DC conditions to minimize the load
regulation issues. A stable control loop has a gain crossing
The ESR of the output capacitor creates a “zero” at the
frequency a shown in Equation 37:
with ? 20 dB/decade slope and a phase margin greater than
45 ° . Include worst ? case component variations when
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