参数资料
型号: NCP3101BUCK2GEVB
厂商: ON Semiconductor
文件页数: 20/26页
文件大小: 0K
描述: EVAL BOARD FOR NCP3101BUCK2G
设计资源: NCP3101BUCK2 EVB BOM
NCP3101BUCK2GEVB Gerber Files
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.5V
电流 - 输出: 6A
输入电压: 5V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP3101
其它名称: NCP3101BUCK2GEVBOS
NCP3101C
C C +
R C +
3
2 * F LC * C C *
) f cross * CO ESR * C OUT
I SS
The cross over combined compensation network can be
used to calculate the transconductance output compensation
network as follows:
1 R 2
* * gm 3 (eq. 46)
F PO R 2 * R 1
1 10 k W
43.3 nF + * * 3.4 mS
18.9 kHz 10 k W ) 31.6 k W
C C = Compensation capacitor
F PO = Pole frequency
gm = Transconductance of amplifier
R 1 = Top of resistor divider
R 2 = Bottom of resistor divider
1
2
2
t SS + 3
1.31 ms +
C P = Compensation pole capacitor
C C = Compensation capacitor
D = Duty ratio
I SS = Soft ? start current
t SS = Soft ? start interval
V ramp = Peak ? to ? peak voltage of the ramp
C P ) C C * D * V ramp
0.309 nF ) 43 nF * 27.5% * 1.1 V
10 m A
V
900 mV
(eq. 50)
5.05 k W +
1
(eq. 47)
Vcomp
2 * 2.35 kHz * 43.3 nF *
2
2
) 27 kHz * 12 m W * 820 m F
C P + C OUT * 3
R C * 2 * p
C C = Compensation capacitance
CO ESR = Output capacitor ESR
C OUT = Output capacitance
f cross = Crossover frequency
F LC = Output inductor and capacitor frequency
R C = Compensation resistor
CO ESR
(eq. 48)
12 m W
309 pF + 820 m F *
5.05 k W * 2 * p
CO ESR = Output capacitor ESR
C OUT = Output capacitor
C P = Compensation pole capacitor
R C = Compensation resistor
Calculating Soft ? Start Time
To calculate the soft start delay and soft start time, the
following equations can be used.
Vout
Figure 31. Soft Start Ramp
The delay from the charging of the compensation network
to the bottom of the ramp is considered t ss delay . The total
delay time is the addition of the current set delay and t ss delay ,
which in this case is 3.2 ms and 3.59 ms respectively, for a
total of 6.79 ms.
Calculating Input Inrush Current
The input inrush current has two distinct stages: input
charging and output charging. The input charging of a buck
stage is usually not controlled, and is limited only by the
input RC network and the output impedance of the upstream
power stage. If the upstream power stage is a perfect voltage
source, then the input charge inrush current can be depicted
as shown in Figure 32 and calculated as:
t SSdelay +
3.59 ms +
C P ) C C * 0.9 V
I SS
0.309 nF ) 43 nF * 0.83 V
10 m A
(eq. 49)
IPK
C P
C C
I SS
= Compensation pole capacitor
= Compensation capacitor
= Soft start current
TIME
Figure 32. Input Charge Inrush Current
The time the output voltage takes to increase from 0 V to a
regulated output voltage is t ss as shown in Equation 50:
http://onsemi.com
20
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