参数资料
型号: NCP3101BUCK2GEVB
厂商: ON Semiconductor
文件页数: 5/26页
文件大小: 0K
描述: EVAL BOARD FOR NCP3101BUCK2G
设计资源: NCP3101BUCK2 EVB BOM
NCP3101BUCK2GEVB Gerber Files
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.5V
电流 - 输出: 6A
输入电压: 5V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP3101
其它名称: NCP3101BUCK2GEVBOS
NCP3101C
Table 3. ELECTRICAL CHARACTERISTICS ( ? 40 ° C < T J < 125 ° C; VCC =12 V, BST ? PHS = 12 V, BST = 12 V, PHS = 24 V,
for min/max values unless otherwise noted).
Characteristic
Power Power Channel
Input Voltage Range
Boost Voltage Range
Conditions
PWRV CC ? GND
V CC ? GND
V BST ? GND
Min
2.7
4.5
4.5
Typ
Max
18
13.2
26.5
Unit
V
V
V
SUPPLY CURRENT
Quiescent Supply Current
Quiescent Supply Current
V FB = 0.85 V V COMP = 0.4 V,
No Switching, V CC = 13.2 V
V FB = 0.85 V V COMP = 0.4 V
No Switching, V CC = 5.0 V
4.1
3.2
mA
mA
V CC Supply Current
V CC Supply Current
Boost Quiescent Current
V FB = V COMP = 1 V, Switching, V CC = 13.2 V
V FB = V COMP = 1 V, Switching, V CC = 5 V
V FB = 0.85 V, No Switching, V CC = 13.2 V
9.1
4.8
63
15
8.0
mA
mA
m A
Shutdown Supply Current
V FB = 1 V, VCOMP= 0 V, No Switching, V CC = 13.2 V
?
4.1
?
mA
UNDER VOLTAGE LOCKOUT
V CC UVLO Threshold
V CC UVLO Hysteresis
BST UVLO Threshold Rising
BST UVLO Threshold Falling
V CC Rising Edge
?
BST Rising
3.8
?
?
?
?
364
3.82
3.71
4.3
?
?
?
V
mV
V
V
SWITCHING REGULATOR
VFB Feedback Voltage,
Control Loop in Regulation
Oscillator Frequency
Ramp ? Amplitude Voltage
Minimum Duty Cycle
0 ° C < T J < 70 ° C, 4.5 V < V CC < 13.2 V
? 40 ° C < T J < 125 ° C, 4.5 < V CC < 13.2 V
0 ° C < T J < 70 ° C, 4.5 V < V CC < 13.2 V
? 40 ° C < T J < 125 ° C, 4.5 < V CC < 13.2 V
0.792
0.788
250
233
0.8
?
0.800
0.800
275
275
1.1
7.0
0.808
0.812
300
317
1.4
?
V
kHz
V
%
Maximum Duty Cycle
88.5
%
TG Falling to BG Rising Delay
BG Falling to TG Rising Delay
V CC = 12 V, T G < 2.0 V, B G > 2.0 V
V CC = 12 V, B G < 2.0 V, T G > 2.0 V
46
41
ns
ns
PWM COMPENSATION
Transconductance
3.1
?
3.5
mS
Open Loop DC Gain
Output Source Current
Output Sink Current
Input Bias Current
Guaranteed by design
V FB < 0.8 V
V FB > 0.8 V
55
80
80
?
70
140
131
0.160
?
200
200
1.0
DB
m A
m A
ENABLE
Enable Threshold (Falling)
0.37
0.4
.43
V
SOFT ? START
Delay to Soft ? Start
1
?
5
ms
SS Source Current
Switch Over Threshold
V FB < 0.8 V
V FB = 0.8 V
?
?
10.6
100
?
?
m A
% of
Vref
OVER ? CURRENT PROTECTION
OCSET Current Source
OC Threshold
OC Switch ? Over Threshold
Fixed OC Threshold
Sourced from BG Pin before Soft ? Start
R BG = 5 k W
?
?
?
?
10
50
700
99
?
?
?
?
m A
mV
mV
mV
PWM OUTPUT STAGE
High ? Side Switch On ? Resistance
Low ? Side Switch On ? Resistance
V CC = 12 V I D = 1 A
V CC = 12 V I D = 1 A
?
?
18
18
?
?
m W
m W
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