参数资料
型号: NCP4331DR2G
厂商: ON Semiconductor
文件页数: 13/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-SOIC
标准包装: 2,500
PWM 型: 控制器
输出数: 2
频率 - 最大: 400kHz
电源电压: 最高 30V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
NCP4331
V out + d n @ @ V in
N P
As portrayed in Figure 21, the post-regulator controls the
energy to be drawn from the power source V in by adjusting
the time during which the high-side MOSFET is on. This
conduction time is modulated by adjusting the leading edge
of the high side drive while the trailing edge stays
synchronized to the input voltage V in .
As in a traditional buck, the post-regulated output voltage
is given by the following equation:
N S
(eq. 2)
forward
Sequencing and Regulation Block
The following timing diagram portrays the sequencing.
V in (Post-Regulator
Input Voltage)
Internal Reset Signal
Where: d n is the duty cycle of the post-regulator n.
d n < d F since (N S /N P ? (V in ) forward ) is available only during
the forward converter on-time and that anyway, the
high-side MOSFET cannot be turn on as long as V in is low
(i.e., during the forward off-time).
Post-regulated output voltages are then necessarily lower
than the main regulated one. However, the NCP4331
scheme allows d n to nearly equal d f so that if necessary, a
post-regulated output voltage (Vout n ) can be very closed the
main one (V out1 ).
TIME
TIME
250 ns
V ramp (C ramp
Timing Ramp)
TIME
TIME
Sum
(V ramp + EA out )
Low-Side Driver
High-Side Driver
70 ns
70 ns
EA out (Error
Amplifier Out
TIME
TIME
TIME
The Low-Side and
High-Side Trans‐
itions are Delayed
until V in is High.
Figure 22. Timing Diagram
Sequencing and Overlapping
Figure 22 portrays the sequencing of a NCP4331 driven
post-regulator.
The high-side driver turns on (off) after some delay just
after the low-side has switched off (on). More precisely, the
high-side MOSFET:
http://onsemi.com
13
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