参数资料
| 型号： | NCP4331DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 最高 30V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP4331
? Turns on 70 ns after the low-side MOSFET opening,
? Turns off 70 ns after the low-side MOSFET closing.
Hence, there are 70 ns when both the high-side and
low-side MOSFETs are on. Such a behavior is possible
because this event occurs just after the input voltage has
dropped to zero (the post-regulator is not the seat of
cross-conduction and instead, as it will be seen in next
sections, this sequencing optimizes the switching
performance), i.e., at the beginning of the forward free
wheeling phase. Hence, no energy can then be drawn from
the converter transformer during this delay and these 70 ns
should not be considered as a part of the high-side MOSFET
conduction time.
Similarly, there are 70 ns during which both MOSFETs
are off, just before the low side conduction phase. During
this short time, the body diode of the low side MOSFET
derives the coil current. Hence, its drain-source voltage is
already low when the low-side MOSFET turns on. The
resulting Zero Voltage Switching optimizes the efficiency.
In light load, the body diode of the high-side MOSFET
may conduct the coil current if it is negative (flowing back
from the load to the input).
Error Amplifier
The NCP4331 embeds an error amplifier. The internal
0.75 V reference is better than $ 1.5% accurate over the 0 ° C
to 85 ° C temperature range ( $ 2% over the 0 ° C to 85 ° C
range). The circuit provides access to its inverting input and
to its output. Typically, the output voltage of the
post-regulator is scaled down by a resistive divider to be
monitored by the inverting input (”FB” pin - Pin 6). The bias
current is minimized (less than 500 nA) to allow the use of
a relatively high impedance feed-back network. The output
of the error amplifier is pinned out for external loop
compensation (Pin 5). Please note that a NCP4331 driven
post-regulator can be viewed as a voltage mode buck
converter and hence, that a type 3 compensation network is
recommended (see application schematic of page 1).
Ramp Generation and PWM Section
An internal current source (I RAMP = 50 m A) charges the
C RAMP timing capacitor to form a ramp that is reset by the
synchronization pin when the input voltage falls down. The
circuit adds the resulting, synchronized saw-tooth (V ramp )
to the error amplifier output (EA OUT ). The PWM
comparator monitors the obtained sum and sets the PWM
latch when this voltage (V ramp + EA OUT ) exceeds the
internal PWM reference (“V PWM ”). As a consequence, the
low-side MOSFET turns off. 70 ns later, the high-side
MOSFET switches on and remains closed until the next
RESET sequence, i.e., when the input voltage drops to zero.
Hence, the raising edge of the high-side MOSFET is
modulated by the moment when the sum crosses the PWM
reference. In other words, the NCP4331 operates in the so
called Leading Edge Modulation. In fact, the PWM latch
cannot be set before the input voltage is in high state. This
is to avoid that the high-side MOSFET is on while there is
no input voltage. Also, this feature prevents the high-side
MOSFET from keeping high in the case of any interruption
in the V IN generation (if the main converter enters some skip
mode or during the system stop). Practically, the input
voltage presence is detected by the “SYNC” pin.
Soft-Start
The voltage reference of the error amplifier is internally
clamped by the voltage of pin 7. A current source
(I SS = 50 m A) flows out of this pin. A capacitor should be
applied to pin7 so that during the startup phase, the pin
voltage slowly ramps up. As a consequence, the error
amplifier output increases in a soft manner. Hence, the
high-side MOSFET duty-cycle smoothly increases and as
a result, this leads to a soft-start and to a reduction of the
stress during this sequence.
A resistor can also be placed between pin 7 and ground to
adjust the maximum duty-cycle of the high-side MOSFET.
Combine the two functions by implementing these two
components in parallel.
If no component is placed in parallel to the capacitor, the
soft-start voltage ramps up until the internal clamp is
activated. At that moment, the soft-start has no limiting
action on the duty-cycle that is only controlled by the error
amplifier and if used, by the auxiliary operational amplifier.
OverLapping and Transitions
V in
C ramp > 2.5 V
HS MOSFET
LS MOSFET
LS Body
Diode
Coil Current I LOAD
t1 t2 t3 t4
Figure 23. Sequencing and Overlaps Management
As portrayed by Figure 23, three transitions over four are
soft:
1. Low-side Turn On (t3) : The synchronization
block detects when the input voltage (V in ) drops to
zero and following this event, it resets the circuit
to prepare it for the next switching period.
Practically, the C RAMP timing capacitor and the
PWM latch are re-initialized and the low-side
MOSFET is turned on. Just before this low-side
transition, the post-regulator input voltage is low
and its high-side MOSFET is still on. As a
consequence, the low-side MOSFET drain
potential is closed to 0 V. Thus the low-side
MOSFET turns on in a Zero Voltage Switching
mode (ZVS). Hence, the energy Qg necessary to
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