参数资料
| 型号： | NCP4331DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 最高 30V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP4331
ELECTRICAL CHARACTERISTICS (V CC = 20 V, V BST = 7 V, HB Grounded, T J = 0 ° C to +125 ° C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
Unit
ERROR AMPLIFIER
V ref
IB FB
BW
G EA
Referenced Voltage Regulation @ Pin 7 Being Open
0 ° C < T J < 85 ° C
-40 ° C < T J < 125 ° C (Guaranteed by Test from 0 ° C < T J < 125 ° C and
Extended to -40 ° C by Design)
Feedback Input Bias Current @ V pin6 = V ref
Gain Bandwidth
Open Loop Voltage Gain
0.738
0.735
-500
-
-
0.750
0.750
-250
4
70
0.762
0.765
0
-
-
V
nA
MHz
dB
EA out
Pin 5 (Compensation) Voltage
V
-EA max
-EA min
V pin6 = 0 V
V pin6 = 1 V
3.50
-
3.70
0.05
-
0.50
I source-EA
Output Source Current @ V pin6 = 0 V
40
65
90
m A
SOFT-START AND MAXIMUM DUTY-CYCLE LIMITATION (D max )
I SS
V SS
EA MIN
EA SS
Source Current @ V SS = 0 V to 3.5 V
Clamp Voltage
Error Amplifier Output @ V pin5 = 0.5 V
Error Amplifier Output @ V pin6 = 0 V and V pin7 = 2 V
40
3.5
-
1.9
50
3.7
0.05
2.0
63
-
0.5
2.1
m A
V
V
V
RAMP CONTROL
I ramp
V rampH
V rampL
C ramp Current Source @ V ramp = 0 V to 3.5 V
C ramp Ramp Clamp
Low Voltage of the Ramp Saw-Tooth
40
3.5
-
50
3.7
-
63
-
100
m A
V
mV
V rampON
Ramp Voltage Enabling the High-Side Driver:
V
@V pin5 = 0.5 V
@ V pin5 = 3.5 V (Min Highest EA Value)
@ V pin5 = 2 V
2.30
-
0.80
2.50
-
1.00
2.65
0
1.20
Q RESET
T RESET
Current Charge Extracted During the RESET Pulse (Note 4)
Delay from SYNC Pin low to Reset Completion (a Falling Pulse Being
5
-
-
200
-
350
nC
ns
Applied to Pin 16)
R RESET
Sink Resistance of Pin 8 during the Reset Time @ I pin8 = 10 mA (This is
-
15
25
W
the Resistance of the Switch that Discharges the C ramp Capacitor during
the Reset Pulse - Capability of 5 nC Min)
SYNCHRONIZATION BLOCK
V SYNC H
H SYNC
V CL-SYNC
T SYNC w HS
Synchronization Comparator Threshold (V pin9 Rising)
Synchronization Comparator Hysteresis
Negative Clamp Voltage of the Synchronization Pin @ I pin16 = 2 mA
Delay From SYNC Pin High to HS_DRV High
(A Rising PUlse Being Applied to Pin 16)
2.4
1.2
-0.3
-
2.5
1.5
-
100
2.6
1.8
0
250
V
V
V
ns
UNDERVOLTAGE DETECTION (UVP)/SHUTDOWN
V UVP L
V UVP H
H UVP
I UVP
IB UVP
Comparator Threshold (V pin4 Being Falling)
Comparator Threshold (V pin4 Being Rising) (Note 5)
Hysteresis of the UVP Comparator
UVP Current Source
Bias Current
1.92
-
-
15
-
2.00
-
40
25
-
2.08
2.20
-
30
0.1
V
V
mV
m A
m A
3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive
to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design.
4. Guaranteed by design. Tested through the R RESET parameter.
5. Guaranteed by characterization and design.
6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically
http://onsemi.com
6
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