参数资料
| 型号： | NCP4331DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 最高 30V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP4331
DETAILED PIN DESCRIPTIONS
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
CSout
CSin-
CSin+
UVP/
STDWN
COMP
FB
Soft-Start/
Dmax
Cramp
SYNC
GND
LS_DRV
VDD
HB
HS_DRV
BST
VCC
Function
Pin 1 is the output of the auxiliary error amplifier embedded in the NCP4331. This allows for the prevention
of excessive coil or load current. Pin 1 can clamp the main error amplifier output. Controlling the coil
current by this auxiliary error amplifier can provide a CCCV characteristic.
Inverting input of the auxiliary error amplifier that is generally used to control the coil current.
Noninverting input of the auxiliary error amplifier that is generally used to control the coil current.
This pin is designed to detect too low input voltage pulses and to turn off both the low-side and high-side
drivers in such a faulty condition. Also, the soft-start pin is grounded so that the circuit smoothly recovers
operation when the detected fault disappears. This UVP detection function features some programmable
hysteresis to avoid erratic turns on and off of the device. Ground Pin 4 to shutdown the part.
This pin makes available the output of the internal error amplifier, for appropriate compensation of the
regulation loop.
Pin 6 is the feed-back pin that must receive a portion of the output voltage to regulate. It is connected to
the inverting input of the internal error amplifier. The regulation reference is better $ 2% over the -40 ° C to
125 ° C temperature range.
Apply a capacitor to Pin 7 to slow down the start-up phase and reduce the stress during this sequence.
Place a resistor between Pin 7 and ground to adjust the maximum duty-cycle of the high-side MOSFET.
Combine the two functions by implementing these two components in parallel.
This pin sources a constant current. Connect a capacitor to create a voltage ramp. This ramp is summed
to the error amplifier output and compared to a constant voltage reference (V PWM ) to adjust the
post-regulator duty-cycle.
This pin is designed to receive a portion of the input voltage, to synchronize the post-regulator activity to
its pulsed input voltage. Also, the high-side drive cannot be high state if the “SYNC” pin voltage is low.
Ground pin of the circuit.
”LS_DRV“ is the driver output of the low-side MOSFET gate.
“VDD” is the circuit power source that is typically provided by the VCC Pin. A 0.1 m F to 1 m F ceramic
capacitor should be connected between this pin and ground for decoupling.
Connect the common node of the two MOSFETs to this pin.
“HS_DRV” is the driver output of the high-side MOSFET gate.
“BST” is the bootstrap pin. A 0.1 m F to 1 m F ceramic capacitor should be connected between this pin and
the “HB” node. The “BST” voltage feeds the high-side driver (“HS_DRV”).
A DC voltage (up to 30 V) must be applied to this pin. This voltage is internally post-regulated down to
7.5 V to provide the V DD voltage that powers the circuit.
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