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| 型号： | NCP5214EVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP5214 |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 设计资源： | NCP5214EVB BOM NCP5214EVB Gerber Files NCP5214EVB Schematic |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 10A |
| 输入电压： | 5V，4.5 ~ 24 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 100Hz ~ 75kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP5214 |
| 其它名称： | NCP5214EVBOS |
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NCP5214
DETAILED OPERATING DESCRIPTION
General
The NCP5214 2?in?1 Notebook DDR Power Controller
combines the efficiency of a PWM controller for the
VDDQ supply, with the simplicity of using a linear
regulator for the VTT termination voltage power supply.
The VDDQ output can be adjusted through the external
potential divider, while the VTT is internally set to track
half VDDQ.
The inclusion of VDDQ power good voltage monitor,
soft?start, VDDQ overcurrent protection, VDDQ
overvoltage and undervoltage protections, supply
undervoltage monitor, and thermal shutdown makes this
device a total power solution for high current DDR memory
system. The IC is packaged in DFN?22.
Control Logic
The internal control logic is powered by VCCA. The IC
is enabled whenever VDDQEN is high (exceed 1.4 V). An
internal bandgap voltage, VREF, is then generated. Once
VREF reaches its regulation voltage, an internal signal
VREFGD will be asserted. This transition wakes up the
supply undervoltage monitor blocks, which will assert
VCCAGD if VCCA voltage is within certain preset levels.
The control logic accepts external signals at VCCA,
OCDDQ, VDDQEN, VTTEN, and FPWM pins to control
the operating state of the VDDQ and VTT regulators in
accordance with Table 1. A timing diagram is shown in
Figure 38.
VDDQ Switching Regulator in Normal Mode (S0)
The VDDQ regulator is a switching synchronous
rectification buck controller directly driving two external
N?Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM with external
compensation and with switching frequency fixed at
400 kHz " 15%. As can be observed from Figure 1, the
Table 1. State, Operation, Input and Output Condition Table
VDDQ output voltage is divided down and fed back to the
inverting input of an internal error amplifier through
FBDDQ pin to close the loop at VDDQ = VFBDDQ ×
(1 + R1/R2). This amplifier compares the feedback voltage
with an internal VREF (= 0.800 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform
derived from the internal oscillator to generate a
pulse?width?modulated signal. This PWM signal drives
the external N?Channel Power FETs via the TGDDQ and
BGDDQ pins. External inductor L and capacitor COUT1
filter the output waveform. The VDDQ output voltage
ramps up at a pre?defined soft?start rate when the IC enters
state S0 from S5. When in normal mode, and regulation of
VDDQ is detected, signal INREGDDQ will go HIGH to
notify the control logic block.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive non?overlap timing control of the
complementary gate drive output signals is provided to
reduce large shoot?through current that degrades
efficiency.
Tolerance of VDDQ
The tolerance of VFBDDQ and the ratio of external
resistor divider R1/R2 both impact the precision of VDDQ.
With the control loop in regulation, VDDQ = VFBDDQ ×
(1 + R1/R2). With a worst case (for all valid operating
conditions) VFBDDQ tolerance of " 1.5%, a worst case
range of " 2.5% for VDDQ = 1.8 V will be assured if the
ratio R1/R2 is specified as 1.2500 " 1%.
Input Conditions
Operating Conditions
Output Conditions
Mode
S5
S5
S0
S3
VCCA
Low
X
High
High
VOCDDQ
X
Low
High
High
VDDQEN
X
X
High
High
VTTEN
X
X
High
Low
FPWM
X
X
X
High
VDDQ
H?Z
H?Z
Normal
Standby
VTTREF
H?Z
H?Z
Normal
Normal
VTT
H?Z
H?Z
Normal
H?Z
TGDDQ
Low
Low
Normal
Standby
BGDDQ
Low
Low
Normal
Standby
PGOOD
Low
Low
H?Z
H?Z
(Power?
saving)
(Power?
saving)
S3
S5
High
X
High
X
High
Low
Low
X
Low
X
Normal
H?Z
Normal
H?Z
H?Z
H?Z
Normal
Low
Normal
Low
H?Z
Low
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