参数资料
型号: NCP5214EVB
厂商: ON Semiconductor
文件页数: 23/32页
文件大小: 0K
描述: EVAL BOARD FOR NCP5214
产品变化通告: Product Obsolescence 24/Jan/2011
设计资源: NCP5214EVB BOM
NCP5214EVB Gerber Files
NCP5214EVB Schematic
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 10A
输入电压: 5V,4.5 ~ 24 V
稳压器拓扑结构: 降压
频率 - 开关: 100Hz ~ 75kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: NCP5214
其它名称: NCP5214EVBOS
NCP5214
BW +
R3 VIN 1
COUT
R3 +
Close loop system bandwidth can be calculated by:
(eq. 28)
R1 VRAMP 2 p L
Since the ramp amplitude of the PWM modulator has a
voltage feedforward function, the ramp amplitude is a
By using the above equations and guidelines, the
compensation components values can be determined by the
equations below:
2 p BW  VRAMP  R1   L  COUT (eq. 30)
VIN
function of V IN which can be determined by:
VRAMP + 1.25 V ) 0.045 (VIN?5.0 V) (eq. 29)
C2 +
2
L
R3
COUT
(eq. 31)
Below are some guidelines for setting the compensation
components:
1. Set a value for R 1 between 2.0 k W and 5.0 k W .
C1 +
C2
R3 C2
ESR COUT
* 1
(eq. 32)
2. Set a target for the close loop bandwidth which
should be less than 50% of the switching
frequency.
R4 +
p
fSW
R1
L
COUT * 1
(eq. 33)
3. Pick compensation DC gain (R 3 /R 1 ) for desired
close loop bandwidth.
C3 +
p
1
R4
fSW
(eq. 34)
4. Place 1st zero at half filter double pole.
5. Place 1st pole at ESR zero.
6. Place 2nd zero at filter double pole.
7. Place 2nd pole at half the switching frequency.
The modulator and filter gain, compensation gain, and
close loop gain asymptotic Bode plot can be drawn by the
calculated results to check the compensation gain and close
loop gain obtained. An example of asymptotic Bode plot is
shown in Figure 40.
The phase of the output filter can be calculated by:
2 p f
L
COUT?1
Phase(Filter) + ? tan ?1(2 p f
ESR
COUT)? tan ?1
2 p f
ESR ) DCR COUT
2
(eq. 35)
where the DCR of the inductor can be neglected if the DCR is small.
The phase of the Type III compensation network can be calculated by:
Phase(TypeIII) + ?90 ° ) tan ?1(2 p f
R3
C2)? tan ?1 2 p f
R3
C1  C2
C1 ) C2
(eq. 36)
) tan ?1(2 p f
(R1 ) R4)
C3)? tan ?1(2 p f
R4
C3)
The close loop phase can be calculated by summing the
filter phase and compensation phase:
R2 +
0.8  R1
VOUT?0.8
(eq. 39)
Phase(CloseLoop) + Phase(Filter) ) Phase(TypeIII)
(eq. 37)
Then the close loop phase margin can be estimated by:
Phase(Margin) + Phase(CloseLoop) * ( * 180 ° )
(eq. 38)
It should be checked that closed loop gain has a 0 dB gain
crossing with ?20 dB/decade slope and a phase margin of
45 ° or greater. The compensation components values may
require some adjustment to meet these requirements.
Besides, the compensation gain should be checked with the
error amplifier open loop gain to make sure that it is
bounded by the error amplifier open loop gain.
The poles and zeros locations and hence the
compensation network components values may need to be
further fine tuned after actual system testing and analysis.
Feedback Resistor Divider
The output voltage of the buck regulator can be adjusted
by the feedback resistor divider formed by R 1 and R 2 . Once
the value of R 1 is selected when determining the
compensation components, the value of R 2 can be obtained
It is recommended to adjust the value of R 2 to fine?tune
the output voltage when it is necessary. The value of R 1
should not be changed since the compensation DC gain and
the 2 nd zero break frequency of the compensation gain are
contributed by R 1 . If the value of R 1 is changed, the
compensation, the close loop bandwidth and phase margin,
and the system stability will be affected. Besides, it is
recommended to use resistors with at least 1% tolerance for
R 1 and R 2 .
Soft?Start of Buck Regulator
A VDDQ soft?start feature is incorporated in the device
to prevent surge current from power supply and output
voltage overshoot during power up. When VDDQEN,
VCCA, and VOCDDQ rise above their respective upper
threshold voltages, the external soft?start capacitor C SS
will be charged up by a constant current source, I ss . When
the soft?start voltage (Vcss) rises above the SS_EN voltage
( X 50 mV), the BGDDQ and TGDDQ will start switching
and VDDQ output will ramp up with VFBDDQ following
the soft?start voltage. When the soft?start voltage reaches
the SS_OK voltage ( X Vref + 50 mV), the soft?start of
by:
http://onsemi.com
23
相关PDF资料
PDF描述
TC4468CPD IC MOSFET DVR QUAD AND 14DIP
TC4423COE IC MOSFET DVR 3A DUAL HS 16-SOIC
GMC08DREN CONN EDGECARD 16POS .100 EYELET
TC4424COE IC MOSFET DVR 3A DUAL HS 16-SOIC
FESB8GT-E3/45 DIODE 8A 400V 50NS SGL TO263AB
相关代理商/技术参数
参数描述
NCP5214MNR2 功能描述:DC/DC 开关控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK
NCP5214MNR2G 功能描述:DC/DC 开关控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK
NCP5215 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Dual Synchronous Buck Controller for Notebook Power System
NCP5215MNR2G 功能描述:直流/直流开关转换器 BUCK CONTROLLER RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT
NCP5217A 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Single Synchronous Step-Down Controller