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参数资料
| 型号： | NCP5214EVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCP5214 |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 设计资源： | NCP5214EVB BOM NCP5214EVB Gerber Files NCP5214EVB Schematic |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 10A |
| 输入电压： | 5V，4.5 ~ 24 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 100Hz ~ 75kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCP5214 |
| 其它名称： | NCP5214EVBOS |
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NCP5214
ILIMIT + RL1
RDS(on)
The maximum drain?to?source voltage rating of the
MOSFETs used in buck converter should be at least 1.2 times
of the maximum input voltage. Generally, V DSS of 30 V
should be sufficient for both high?side MOSFET and
low?side MOSFET of the buck converter for notebook
application.
As a general rule of thumb, the gate charges are the
smaller; the better is the MOSFET while R DS(on) is still low
enough. MOSFETs are susceptible to false turn?on under
high dV/dt and high VDS conditions. Under high dV/dt and
high V DS condition, current will flow through the C GD of
the capacitor divider formed by C GD and C GS , cause the
C GS to charge up and the V GS to rise. If the V GS rises above
the threshold voltage, the MOSFET will turn on.
Therefore, it should be checked that the low?side MOSFET
have low Q GD to Q GS ratio. This indicates that the low?side
MOSFET have better immunity to short moment false
turn?on due to high dV/dt during the turn?on of the
high?side MOSFET. Such short moment false turn?on will
cause minor shoot?through current which will degrade
efficiency, especially at high input voltage condition.
Overcurrent Protection of VDDQ Buck Regulator
The OCP circuit is configured to set the current limit for
the current flowing through the high?side FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the high?side FET.
An internal 31 m A current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC and develops a voltage at the
non?inverting input of the current limit comparator.
Another voltage drop is established across the high?side
MOSFET R DS(on) at a magnitude of I L xR DS(on) and a
voltage is developed at SWDDQ when the high?side
MOSFET is turned on and the inductor current flows
through the R DS(on) of the MOSFET. The voltage at the
non?inverting input of the current limit comparator is then
compared to the voltage at SWDDQ pin when the
high?side gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than the voltage at the
non?inverting input of the current limit comparator for four
consecutive internal clock cycles, an overcurrent condition
occurs, during which, all outputs will be latched off to
protect against a short?to?ground condition on SWDDQ or
VDDQ. i.e., the voltage drop across the R DS(on) of
high?side FET developed by the drain current is larger than
the voltage drop across RL1, the OCP is triggered and the
device will be latched off.
The overcurrent protection will trip when a peak inductor
current hit the I LIMIT determined by the equation:
IOC
(eq. 19)
It should be noted that the OCDDQ pin must be pulled
high to VIN through a resistor RL1 and this pin cannot be
left floating for normal operation. The voltage drop across
RL1 must be less than 1.0 V to allow enough headroom for
the voltage detection at the OCDDQ pin under low VIN
condition. In addition, since the MOSFET R DS(on) varies
with temperature as current flows through the MOSFET
increases, the OCP trip point also varies with the MOSFET
R DS(on) temperature variation.
Since the IOC and R DS(on) have device variations and
MOSFET R DS(on) increase with temperature, to avoid false
triggering the overcurrent protection in normal operating
output load range, calculate the RL1 value from the
previous equation with the following conditions such that
minimum value of inductor current limit is set:
1. The minimum IOC value from the specification
table.
2. The maximum R DS(on) of the MOSFET used at
the highest junction temperature.
3. Determine I LIMIT for I LIMIT > I LOAD(max) +
I L(ripple)/ 2, where I LOAD(max) = I VDDQ(max) +
I VTT(max) if VTT is powered by VDDQ.
Besides, a decoupling capacitor C DCPL should be added
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the high?side MOSFET.
Loop Compensation
Once the output LC filter components have been
determined, the compensation network components can be
selected. Since NCP5214 is a voltage mode PWM
converter with output LC filter, Type III compensation
network is required to obtain the desired close loop
bandwidth and phase boost with unconditional stability.
The NCP5214 PWM modulator, output LC filter and
Type III compensation network are shown in Figure 39.
The output LC filter has a double pole and a single zero.
The double pole is due to the inductance of the inductor and
capacitance of the output capacitor, while the single zero
is due to the ESR and capacitance of the output capacitor.
The Type III compensation has two RC pole?zero pairs.
The two zeros are used to compensate the LC double pole
and provide 180 ° phase boost. The two poles are used to
compensate the ESR zero and provide controlled gain
roll?off. For an ideally compensated system, the Bode plot
should have the close?loop gain roll?off with a slope of
?20 dB/decade crossing the 0 dB with the required
bandwidth and the phase margin larger than 45 ° for all
frequencies below the 0 dB frequency. The closed loop
gain is obtained by adding the modulator and filter gain (in
dB) to the compensation gain (in dB) . The bandwidth is the
frequency at which the gain is 0 dB and the phase margin
is the difference between the close loop phase and 180 ° .
The goal of compensation is to achieve a stable close loop
system with the highest possible bandwidth, the gain
having ?20 dB/decade slope at 0 dB gain crossing, and
sufficient phase margin for stability. The bandwidth of
close loop gain should be less than 50% of the switching
frequency and the compensation gain should be bounded
by the error amplifier open loop gain.
http://onsemi.com
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| NCP5214MNR2 | 功能描述:DC/DC 开关控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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